Donghee Lee

On the existence of a spectrum of policies that subsumes the least recently used (LRU) and least frequently used (LFU) policies

Sam H. Nohs Sang Lyul Mint t Department of Computer Engineering Seoul National University Seoul 151-742, Korea http://ssrnet.snu.ac.kr http://archi.snu.ac.kr We show that there exists a spectrum of block replacement policies that subsumes both the Least Recently Used (LRU) and the Least Frequently Used (LFU) policies. The spectrum is formed according to how much more weight we give to the recent history than to the older history, and is referred to as the LRFU (Least Recently/Frequently Used) policy. Unlike many previous policies that use limited history to make block replacement decisions, the LRFU policy uses the complete reference history of blocks recorded during their cache residency. Nevertheless, the LRFU requires only a few words for each block to maintain such history. This paper also describes an implementation of the LRFU that again subsumes the LRU and LFU implementations. The LRFU policy is applied to buffer caching, and results from trace-driven simulations show that the LRFU performs better than previously known policies for the workloads we considered. This point is reinforced by results from our integration of the LRFU into the FreeBSD operating system.

Disk schedulers for solid state drivers

In embedded systems and laptops, flash memory storage such as SSDs (Solid State Drive) have been gaining popularity due to its low energy consumption and durability. As SSDs are flash memory based devices, their performance behavior differs from those of magnetic disks. However, little attention has been paid on how to exploit SSDs from the disk scheduling algorithm view point. In this paper, we first describe behaviors of SSDs that inspires us to design a new disk scheduler for the Linux operating system. Specifically, read service time is almost constant in an SSD while write service time is not. Moreover, appropriate grouping of write requests eliminates any ordering-related restrictions and also maximizes write performance. From these observations, we propose two disk schedulers: IRBW-FIFO and IRBW-FIFO-RP. Both schedulers arrange write requests into bundles of an appropriate size while read requests are independently scheduled. Then, the IRBW-FIFO scheduler provides complete FIFO ordering to each bundle of write requests and each individual read requests while the IRBW-FIFO-RP scheduler gives higher priority to read requests than the bundles of write requests. We implement these schedulers in Linux 2.6.23, and results of executing our set of benchmark programs shows that performance improvements of up to 17% compared to existing Linux disk schedulers are achieved.

Exploiting non-volatile RAM to enhance flash file system performance

Non-volatile RAM (NVRAM) such as PRAM (Phase-change RAM), FeRAM (Ferroelectric RAM), and MRAM (Magnetoresistive RAM) has characteristics of both non-volatile storage and random access memory (RAM). These forms of NVRAM are currently being developed by major semiconductor companies and are expected to be an everyday component in the near future. The advent of NVRAM may possibly bring about drastic changes to the system software landscape. In this work, we develop a new Flash memory based file system that exploits NVRAM in order to improve system performance. Specifically, we discuss the initial design and implementation of a file system that stores all metadata in NVRAM, while storing all file data in Flash memory. In so doing, we make two contributions in this work. First, we present a model that analyzes the amount of NVRAM that is needed for specific Flash memory storage capacity. Experimentally, we verify that this model represents the exact NVRAM usage in the realistic environment. Second, we present quantitative experimental results that show how much performance gains are possible by exploiting NVRAM. Compared to YAFFS, a popular Flash memory based file system, we show that this file system requires only minimal time for mounting and that the execution time improves by a maximum of 600% and an average of 437% for the realistic workloads that we considered.

Block recycling schemes and their cost-based optimization in nand flash memory based storage system

Flash memory has many merits such as light weight, shock resistance, and low power consumption, but also has limitations like the erase-before-write property. To overcome such limitations and to use it efficiently as storage media in mobile systems, Flash memory based storage systems require special address mapping software called the FTL (Flash-memory Translation Layer). Like cleaning in Log-structured file system (LFS), the FTL often performs a merge operation for block recycling and its efficiency affects the performance of the storage system. To reduce the block recycling costs in NAND Flash memory based storage, we introduce another block recycling scheme that we call migration. Our cost-models and experimental results show that cost-based selection of merge or migration for each block recycling can decrease block recycling costs and, therefore, improve performance of Flash memory based storage systems. Also, we derive the macroscopic optimal migration/merge sequence minimizing block recycling costs for each migration/merge combination period. Experimental results show that the performance of Flash memory based storage can be further improved by the macroscopic optimization than the simple cost-based selection.

Regularities considered harmful: forcing randomness to memory accesses to reduce row buffer conflicts for multi-core, multi-bank systems

We propose a novel kernel-level memory allocator, called M3 (M-cube, Multi-core Multi-bank Memory allocator), that has the following two features. First, it introduces and makes use of a notion of a memory container, which is defined as a unit of memory that comprises the minimum number of page frames that can cover all the banks of the memory organization, by exclusively assigning a container to a core so that each core achieves bank parallelism as much as possible. Second, it orchestrates page frame allocation so that pages that threads access are dispersed randomly across multiple banks so that each threads access pattern is randomized. The development of M3 is based on a tool that we develop to fully understand the architectural characteristics of the underlying memory organization. Using an extension of this tool, we observe that the same application that accesses pages in a random manner outperforms one that accesses pages in a regular pattern such as sequential or same ordered accesses. This is because such randomized accesses reduces inter-thread access interference on the row-buffer in memory banks. We implement M3 in the Linux kernel version 2.6.32 on the Intel Xeon system that has 16 cores and 32GB DRAM. Performance evaluation with various workloads show that M3 improves the overall performance for memory intensive benchmarks by up to 85% with an average of about 40%.

Janus-FTL: finding the optimal point on the spectrum between page and block mapping schemes

NAND flash memory based storage such as SSDs is gaining popularity in commodity computer systems. Some low-end SSDs use the block mapping FTL (Flash Translation Layer) that is good for sequential write patterns but poor for random ones. On the other hand, high-end SSDs tend to use the page mapping FTL that is effective for random write patterns, but whose performance degrades after successive random writes. Designing an FTL that adapts to various workload patterns and provides long-term stable performance is a challenging issue. To resolve this issue, we propose a new FTL, which we call Janus-FTL, that provides a spectrum between the block and page mapping schemes. By adapting along the spectrum, Janus-FTL can provide long-term superior write performance for various workload patterns. We also present a cost model of Janus-FTL that shows the existence of the optimal point on the spectrum for a given workload. Our experimental results show the superiority of Janus-FTL, which adapts itself along the spectrum for a given workload, over state-of-the-art hybrid mapping FTLs and the pure page mapping FTL

Improving SSD reliability with RAID via Elastic Striping and Anywhere Parity

While the move from SLC to MLC/TLC flash memory technology is increasing SSD capacity at lower cost, it is being done at the cost of sacrificing reliability. An approach to remedy this loss is to employ the RAID architecture with the chips that comprise SSDs. However, using the traditional RAID approach may result in negative effects as the total number of writes may increase due to the parity updates, consequently leading to increased P/E cycles and higher bit error rates. Using a technique that we call Elastic Striping and Anywhere Parity (eSAP), we develop eSAP-RAID, a RAID scheme that significantly reduces parity writes while providing reliability better than RAID-5. We derive performance and lifetime models of SSDs employing RAID-5 and eSAP-RAID that show the benefits of eSAP-RAID. We also implement these schemes in SSDs using DiskSim with SSD Extension and validate the models using realistic workloads. Our results show that eSAP-RAID improves reliability considerably, while limiting its wear. Specifically, the expected lifetime of eSAP-RAID employing SSDs may be as long as current ECC based SSDs, while its reliability level can be maintained at the level of the early stages of current ECC based SSDs throughout its entire lifetime.

CPS-SIM: configurable and accurate clock precision solid state drive simulator

NAND flash memory is the most widely used storage medium in embedded systems today due to its many advantages such as light weight, low power consumption, and shock resistance. Recently, solid state drives (SSDs), which use NAND flash memory to store data, are replacing conventional magnetic disks in laptops and some server computers. In the SSDs, to achieve both high performance and large capacity, a number of flash memory chips are connected to multiple buses and SSD firmware exploits parallel accesses by using interleaving and overlapping techniques. However, it is still unclear how many buses or chips should be used and how to drive those chips and buses to satisfy performance that may be required. To help answer these questions, we have developed a clock precision SSD simulator (CPS-SIM) that simulates the internal behavior of an SSD and that reports timing and utilization information. From the accurate timing and utilization results of CPS-SIM, we can discover the optimal hardware configuration including the number of buses and chips and their interconnections in an SSD. Also, it allows for fast development and verification of SSD firmware that runs an FTL (Flash Translation Layer) optimized for an SSD. Unlike FTLs for embedded flash memory, the FTL for an SSD must utilize the concurrency of the multiple chips and buses. By supporting concurrency, our CPS-SIM provides a flexible environment for design of SSD firmware that drives the multiple flash memory chips and also that schedules data transmissions via the multiple buses.

Implementation and performance evaluation of the LRFU replacement policy

Recently, a new block replacement policy called the LRFU (Least Recently/Frequently Used) policy was proposed that subsumes both the LRU and LFU policies, and provides a spectrum of replacement policies between them. We describe an implementation of the LRFU replacement policy in the FreeBSD 2.1.5 and present a performance evaluation of the implementation using the SPEC SDET benchmark. The results show that the new policy gives up to a 30% performance improvement over the LRU block replacement policy.

Models and Design of an Adaptive Hybrid Scheme for Secure Deletion of Data in Consumer Electronics

As more mobile storage devices are used in consumer electronics, possibility of user confidential data leakage increases. To make things worse, data of deleted file in mobile storage such as USB drives can be easily recovered and, thus, can be vulnerable to data leakage. To prevent this type of data leakage, efficient secure deletion techniques are required and we present two secure deletion techniques, namely block cleaning and zero overwriting, for flash memory storage. Also, we propose cost and benefit models of both techniques. The models imply an existence of an efficient adaptive hybrid secure deletion scheme that applies one of the techniques based on their costs and benefits at given data arrangements. Experimental results measured on an embedded board show that the adaptive hybrid scheme deletes data securely and efficiently for various data patterns on flash memory storage.