Jongsu Yi

Real-Time Three Dimensional Vision

Active systems for collision avoidance in ‘noisy’ environments such as traffic which contain large numbers of moving objects will be subject to considerable interference when the majority of the moving objects are equipped with common avoidance systems. Thus passive systems, which require only input from the environment, are the best candidates for this task. In this paper, we investigate the feasibility of real-time stereo vision for collision avoidance systems. Software simulations have determined that sum-of-absolute-difference correlation techniques match well but hardware accelerators are necessary to generate depth maps at camera frame rates. Regular structures, linear data flow and abundant parallelism make correlation algorithms good candidates for reconfigurable hardware. The SAD cost function requires only adders and comparators for which modern FPGAs provide good support. However accurate depth maps require large disparity ranges and high resolution images and fitting a full correlator on a single FPGA becomes a challenge. We implemented SAD algorithms in VHDL and synthesized them to determine resource requirements and performance. Altering the shape of the correlation window to reduce its height compared to its width reduces storage requirements with negligible effects on matching accuracy. Models which used the internal block memory provided by modern FPGAs to store the ‘inactive’ portions of scan lines were compared with simpler models which used the logic cell flip-flops. From these results, we have developed a simple predictor which enables one to rapidly determine whether a target appliction is feasible.

A pattern-based prediction: An empirical approach to predict end-to-end network latency

Understanding latency in network-based applications has received considerable attention to provide consistent and acceptable levels of services. This paper presents an empirical approach, a pattern-based prediction method, to predict end-to-end network latency. The key idea of the approach is to utilize past history of latency and their variation patterns in latency predictions. After some preliminary study on simple numerical prediction models we examine the effectiveness of the proposed method with real latency data and various definitions of network stability. Our results show that the pattern-based method outperforms any single numerical model obtaining an overall prediction accuracy of 86.2%.

A Platform-Based SoC Design for Real-Time Stereo Vision

A stereo vision is able to build three- dimensional maps of its environment. It can provide much more complete information than a 2D image based vision but has to process, at least, that much more data. In the past decade, real-time stereo has become a reality. Some solutions are based on reconfigurable hardware and others rely on specialized hardware. However, they are designed for their own specific applications and are difficult to extend their functionalities. This paper describes a vision system based on a System on a Chip (SoC) platform. A real-time stereo image correlator is implemented using Sum of Absolute Difference (SAD) algorithm and is integrated into the vision system using AMBA bus protocol. Since the system is designed on a pre-verified platform it can be easily extended in its functionality increasing design productivity. Simulation results show that the vision system is suitable for various real-time applications

Design a Switch Wrapper for SNA On-Chip-Network

In this paper we present a design of a switch wrapper as a component of SNA (SoC Network Architecture), which is an efficient on-chip-network compared to a shared bus architecture in a SoC. The SNA uses crossbar routers to provide the increasing demand on communication bandwidth within a single chip. A switch wrapper for SNA is located between a crossbar router and IPs connecting them together. It carries out a mode of routing to assist crossbar routers and executes protocol conversions to provide compatibility in IP reuse. A switch wrapper consists of a direct router, two AHB-SNP converters, a controller and two optional interface socket modules. We implemented a SNP switch wrapper in VHDL and confirmed its functionality using ModelDim simulation. Also, we synthesized it using a Xilinx Virtex2 device to determine resource requirements: the switch wrapper seems to occupy appropriate spaces, about 900 gates, considering that a single SNA crossbar router costs about 20,000 gates.

A switch wrapper design for SNA on-chip-network

In this paper we present a design of a switch wrapper as a component of SNA (SoC network architecture), which is an efficient on-chip-network compared to a shared bus architecture in a SoC. The SNA uses crossbar routers to provide the increasing demand on communication bandwidth within a single chip. A switch wrapper for SNA is located between a crossbar router and IPs connecting them together. It carries out a mode of routing to assist crossbar routers and executes protocol conversions to provide compatibility in IP reuse. A switch wrapper consists of a direct router, two AHB-SNP converters, two interface sockets and a controller module. We implement it in VHDL. Using ModelSim simulation, we confirm the functionality of the switch wrapper. We synthesize it using a Xilinx Virtex2 device to determine resource requirements: The switch wrapper seems to occupy appropriate spaces, about 900 gates, considering that a single SNA crossbar router costs about 20,000 gates.