Joon-seok Park

Characteristics of Double-Gate Ga–In–Zn–O Thin-Film Transistor

A Ga-In-Zn-O thin-film transistor with double-gate structure is reported. Enhancement-mode operation that is essential to the constitution of a low-power digital circuitry is easily achieved when the upper and lower gate electrodes are tied together. The saturation mobility and the subthreshold swing are improved from 3.65 cm2/(V·s) and 0.44 V/dec to 18.9 cm2/(V·s) and 0.14 V/dec, respectively, compared with the single-gate structure. We can modulate the threshold voltage of either gate by adjusting the bias on the other gate.

Highly Stable Double-Gate Ga–In–Zn–O Thin-Film Transistor

We report the electrical stability of double-gate (DG) Ga-In-Zn-O thin-film transistors (TFTs). The threshold voltage (<i>VT</i>) shift of the DG TFT after 3 h of positive-bias temperature stress (<i>V</i>_GS = + 20 V, <i>V</i>_DS = + 0.1 V, and Temperature = 60°C) is as small as +2.7 V, while that of a conventional single-gate (SG) TFT is +6.6 V. The results of negative-bias temperature stress [(NBTS); <i>V</i>_GS = - 20 V, <i>V</i>_DS = + 10 V, and Temperature = 60°C] are more dramatic: The <i>VT</i> shift of the DG TFT is only +0.1 V, whereas that of the SG TFT is -9.1 V. With backlight illumination, the <i>VT</i> shift of the SG TFT under the same NBTS becomes severe ( -11.1 V). However, it remains as small as -0.7 V for the DG TFT.

Performance and area modeling of complete FPGA designs in the presence of loop transformations

Selecting which program transformations to apply when mapping computations to FPGA-based computing architectures can lead to prohibitively long design space exploration cycles. An alternative is to develop fast, yet accurate, performance and area models to quickly understand the Impact and interaction of the transformations. In this paper, we present a combined analytical performance and area modeling approach for complete FPGA designs in the presence of loop transformations. Our approach takes into account the impact of input/output memory bandwidth and memory interface resources, often the limiting factor in the effective implementation of computations. Our preliminary results reveal that our modeling is very accurate, being therefore amenable to be used in a compiler tool to quickly explore very large design spaces.