Jordane Lorandel

Dynamic and Partial Reconfiguration Power Consumption Runtime Measurements Analysis for ZYNQ SoC Devices

Field Programmable Gate Array (FPGA) architectures, such as Xilinxs Virtex-4 up to 7 series, have enabled partial and dynamic run-time self-reconfiguration for a long time. This feature enables the substitution of parts of a hardware design implemented on this re-configurable hardware, and therefore makes it possible for a system to adapt to the actual demands of applications. Dynamic Partial Reconfiguration (DPR) is an interesting technique that permits to share a part of the FPGA between different dedicated functions or hardware accelerators. Many domains may benefit from this technique including the Internet of Things (IoT), automotive industry, etc. However, many parameters, such as reconfiguration overhead, idle power consumption and performance trade-off, must be considered. In this paper, we provide a precise estimation of the power consumption when the DPR process is running in order to evaluate its influence on the performance of the global design. For this purpose, a Software/Hardware (SW/HW) system was implemented and the results were extracted in real-time using Zynq System on Chip SoC devices.

Dynamic power estimation based on switching activity propagation

A new power estimation approach based on the decomposition of a digital system into basic operators is presented. This approach aims to estimate the energy consumption at early design phases of digital blocks implemented on FPGAs. Each operator has its own model which estimates the switching activity and the power consumption. By interconnecting several operators, statistical information is then propagated to provide a global power estimation of a given system. A simple sum of the power dissipation contribution of each operator is enough to compute the total power consumption. This is performed by taking into account the switching activities relative to a given input pattern. Earlier, faster and more flexible power analysis for system designers are the advantages. This approach has been evaluated in a use-case application. The preliminary results indicate a promising speed-up of the design process and an error which is less than 8.0% compare to the classical power estimation tools.

Power estimation on FPGAs based on signal information propagation through digital operators

Today, communicating devices are widespread and the IoT trend tends to make them incontrovertible in our everyday life. According to some forecast, 50 billions of these devices should be available by 2020. The first consequence is that this massive advent of connecting devices will have a huge impact on the world energy consumption. In this context, it is then mandatory to deal with power as soon as possible in the design process of such systems. This paper presents a new power estimation approach at early design phases which is based on the decomposition of a digital system into a set of basic operators. Each operator has its own model which estimates both switching activity and power consumption. By interconnecting several operators, statistical information is then propagated to enable a global power estimation of a given system. The methodology has been evaluated on a simple use-case. The preliminary results indicate a promising speedup of the design process with less than 8.0% of error compare to classical power estimation tools.

Dynamic power evaluation of LTE wireless baseband processing on FPGA

Mobile networks and user equipments continuously evolve to circumvent the data traffic growth and the increasing number of users. However, the complexity and heterogeneity of such systems (3G, LTE, LTE-A, etc.) makes power one of the most critical metric. In this context, power estimation has become an unavoidable task in the design process. In this paper, a dynamic power estimation methodology for FPGA-based systems is presented. It aims at providing accurate and fast power estimations of an entire system prior to its implementation. It also aims at making design space exploration easier. We introduce an innovative scenario-level in order to facilitate the comparison of domain-specific systems. We show the effectiveness of our approach on several LTE baseband configurations which leads to a low absolute error, compared to classic estimations. It also exhibits a high speed-up factor which is determinant during design space exploration.