Jörg Vollrath

Compressed bit fail maps for memory fail pattern classification

Process optimization in a manufacturing environment for dynamic random access devices (DRAMS) can be improved using fail bit maps in production. Since fail bit maps for 64 Mbit, 256 Mbit and 1 Gbit are quite huge, it is difficult to generate, store and analyze these maps in a manufacturing environment. This paper presents a new scheme for generating compressed bit fail maps during test or from full bit fail maps with minimum loss of fail pattern information. Construction of the special compression scheme for a typical memory array with typical fail patterns will be shown. The described method has been successfully implemented for a 64 Mbit DRAM in a manufacturing environment compressing the bit fail maps to 2 kBit, allowing classification of 13 fail types.

Pseudo fail bit map generation for RAMs during component test and burn-in in a manufacturing environment

Bit fail maps of semiconductor memories are generated in a manufacturing environment during wafer test to identify process problems and for repair. Since bit fail map capabilities are expensive for high-speed testers and massive parallel test systems, component test is generating only pass/fail information. It is difficult to relate the pass/fail information to a process problem. This paper presents a test strategy and a software tool to construct pseudo bit fail maps from pass/fail information using a special test sequence. The pseudo bit fail map can be generated in a manufacturing environment and can be used for identifying process problems and doing physical failure analysis at the fail location.

Signal margin analysis for DRAM sense amplifiers

The sense amplifier (SA) design and the bit line architecture determine the minimum detectable signal limit for a dynamic random access memory (DRAM) cell readout operation. Increasing memory sizes, smaller feature sizes and lower operating voltages make it more important to understand the cell signal sensing operation, the signal of memory cells and the limiting factors. This paper presents a measurement method to evaluate the signal created by the memory cell and the sense amplifier uniformity at product level. Measurements of the sense amplifier offset distribution and sense amplifier signals for 0s and 1s for all memory cells will be presented. Spatial analysis gives further insight into the sensing limitations. This can be used to improve the circuit modeling of the sense amplifier and to simulate process variations. The results for a 64Mbit 0.19 /spl mu/m memory device will be shown, having a sense amplifier imbalance.

DRAM-Specific Space of Memory Tests

DRAM testing has always been theoretically considered as a subset of general memory testing, despite the disagreement of this assumption with the DRAM test practice. This paper presents a recently developed space of DRAM faults that describes the unique aspects of DRAM behavior, it validates this fault space using extensive Spice simulation, and it identifies the memory tests necessary to detect these faults. Six different tests are derived and shown to correspond to highly effective DRAM tests in practice

Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach

Fabrication process improvements and technology scaling results in modifications in the characteristics and in the behavior of manufactured memory chips, which also modifies the faulty behavior of the memory. This paper introduces an analytical (equation-based) method to give a rough analysis of the faulty behavior of cell opens in the memory, that simplifies the understanding and identifies the major factors responsible for the faulty behavior. Having these factors makes it easier to optimize the circuit and allows extrapolation of the behavior of future technologies. The paper also compares the results of the analytical approach with those from the simulation-based analysis and discusses the advantages and disadvantages of both