Jorge Luiz e Silva

A Benchmark Approach for Compilers in Reconfigurable Hardware

High-performance FPGA accelerating software applications are a growing demand in fields as communications, image processing, and scientific computing among others. Moreover, as the cost per gate of FPGAs declines, embedded and high-performance systems designers are being presented with new opportunities for creating accelerated software applications using FPGA-based programmable hardware platforms. Powerful high-level language to RTL generators are now emerging. One of the promises of these tools is to allow software and systems engineers to implement algorithms quickly in a familiar language and target the design to a programmable device. The generators available today support syntaxes with different degrees of fidelity to the original language. This paper focuses on the efficient use of C to RTL generators that have a high degree of fidelity to the original C language. The objective of this project is to study some tools that starting from languages of high level as ANSI-C, and generate FPGA accelerating software applications automatically. In this paper are presented tools and partial results of the hardware generated by them

Genetic Algorithms and Artificial Neural Networks to Combinational Circuit Generation on Reconfigurable Hardware

Operating in critical environments is an extremely desired feature for fault-tolerant embedded systems. In addition, due to design test and validation complexity of these systems, faster and easier development methods are needed. Evolvable Hardware (EHW) is a development technique that, using reconfigurable hardware, builds systems that reconfiguration part is under the control of an Evolutionary Algorithm. Reconfigurable hardware allows EHW to change its own hardware structure adapting itself to task and/or environment changes. Evolvable part of these systems can also be implemented using Artificial Neural Networks (ANNs). This research work presents results and comparisons between Genetic Algorithm (GA) and ANN implementations that receive combinational circuits’ truth-tables as input and searches the minimum circuit respecting this input truth-table. GA improved for this work’s EHW structure achieve good execution time for tested tables and ANN modeling presents some non-desired characteristics with bad results.

The ChipCflow: A Tool to Generate Hardware Accelerators Using a Static Dataflow Machine Designed for a FPGA

The execution of sections of algorithms in hardware accelerators, appears as a alternative to speed up performance with low power consumption. In this article the Chip flow project is presented, the goal of Chip flow is conversion of C code in a static dataflow machine designed for a FPGA. The conversion process is discussed and some initial results are presented. The results of Chip flow are compared with a Intel core i7 processor and modern GPU. The results of benchmarks implemented show that Chip flow is a newer alternative for the development of hardware accelerators, with a good performance with low power consumption.

Research and Partial analysis of overhead of a partition model for a Partially Reconfigurable hardware in a data-driven machine - chicflow

Computer applications have become increasingly more complex and require greater processing capacity. In order to achieve higher performance for these applications, algorithms are often implemented in Field-Programmable Gate Arrays (FPGAs). However, most of the Computer-Aided Design (CAD) tools still uses Hardware Description Languages (HDL), which are complex if compared with imperative High Level Languages (HLL). ChipCflow is a tool that aims to convert HLL to HDL, using the dynamic dataflow model and Active Partial Reconfiguration (APR). In this paper we present a research report for the hardware architectures partition model, necessary for the correct allocation of Dataflow Graphs (DFGs) into FPGAs fabric using APR. In order to calculate systems logic overhead, we show some results which denotes a ratio between the operators logic and the necessary reconfigurable area, as well as some guidelines about the reconfiguration time of these reconfigurable areas.

Chipcflow- A dynamic dataflowmachine using dynamic reconfigurable hardware

In order to convert High Level Language (HLL) into hardware, a Control Dataflow Graph (CDFG) is a fundamental element to be used. Otherwise, Dataflow Architecture, can be obtained directly from the CDFG. In the 1970s and late 1980s, the Dataflow Model was the focus of attention that provided parallelism in a natural form. In particular, dynamic dataflow architecture can be generated to produce a high level of parallelism. In this paper, the ChipCflow project is described as a system to convert HLL into a dynamic dataflow graph to be executed in a dynamic reconfigurable hardware, exploring the dynamic reconfiguration. The ChipCflow consists of various parts: the compiler to convert the C program into a dataflow graph; the operators and its instances; the tagged-token; and the matching data. Some results are presented in order to show a proof of concept for the project.

Execution of algorithms using a Dynamic Dataflow Model for Reconfigurable Hardware - A purpose for Matching Data

The dynamic dataflow model in a reconfigurable hardware is a project of an architecture that explores the parallelism in a natural form, using the characteristics of the partial reconfigurable hardware. This project has been developed, and there are results of proof-of-concepts for a protocol between the operators. Specifically on this part of the project is the purpose to matching data into the operators. This paper describes the structure for the matching data