Jørgen Andreas Michaelsen

Evolving self-adaptive services using planning-based reflective middleware

Self-adaptive systems often use a middleware-based approach where adaptation mechanisms and policies are separated and externalized from the application code. Such separation facilitates the independent analysis of application and adaptation. In the QuA middle-ware, we use mirror-based reflection and service planning to support the development and execution of self-adaptive systems. A mirror provides meta information about a services behavior and implementation throughout all life-cycle phases, including its performance in different contexts. Service planning supports dynamic discovery, utility-based and context-aware evaluation, and selection of alternative implementations of a given service.Here we argue that the QuA middleware is also able to support certain forms of evolution of adaptive systems. Since in QuA new implementation alternatives or updated versions of software are automatically discovered and considered during service planning, evolution both during run time and load time is supported. Experimental results from evolving a state-of-the-art adaptive media streaming application using our middleware are also presented.

Exploiting content-based networking for fine granularity multireceiver video streaming

Efficient delivery of video data over computer networks has been studied extensively for decades. Still, multi-receiver video delivery represents a challenge. The challenge is complicated by heterogeneity in network availability, end node capabilities, and receiver preferences. This paper demonstrates that content-based networking is a promising technology for efficient multi-receiver video streaming. The contribution of this work is the bridging of content-based networking with techniques from the fields of video compression and streaming. In the presented approach, each video receiver is provided with fine grained selectivity along different video quality dimensions, such as region of interest, signal to noise ratio, colors, and temporal resolution. Efficient delivery, in terms of network utilization and end node processing requirements, is maintained. A prototype is implemented in the Java programming language and the software is available as open source. Experimental results are presented which demonstrate the feasibility of our approach.

Exploiting content-based networking for video streaming

This technical demonstration shows that content-based networking is a promising technology for multireceiver video streaming. Each video receiver is provided with fine grained selectivity along different video dimensions, such as region of interest, quality, colors, and temporal resolution. Efficient delivery is maintained, in terms of network utilization and processing requirements. A prototype demonstrates the feasibility of this approach and is available as open source.

Real-time video content analysis: QoS-aware application composition and parallel processing

Real-Time content-based access to live video data requires content analysis applications that are able to process video streams in real-time and with an acceptable error rate. Statements such as this express quality of service (QoS) requirements. In general, control of the QoS provided can be achieved by sacrificing application quality in one QoS dimension for better quality in another, or by controlling the allocation of processing resources to the application. However, controlling QoS in video content analysis is particularly difficult, not only because main QoS dimensions like accuracy are nonadditive, but also because both the communication- and the processing-resource requirements are challenging.This article presents techniques for QoS-aware composition of applications for real-time video content analysis, based on dynamic Bayesian networks. The aim of QoS-aware composition is to determine application deployment configurations which satisfy a given set of QoS requirements. Our approach consists of: (1) an algorithm for QoS-aware selection of configurations of feature extractor and classification algorithms which balances requirements for timeliness and accuracy against available processing resources, (2) a distributed content-based publish/subscribe system which provides application scalability at multiple logical levels of distribution, and (3) scalable solutions for video streaming, filtering/transformation, feature extraction, and classification.We evaluate our approach based on experiments with an implementation of a real-time motion vector based object-tracking application. The evaluation shows that the application largely behaves as expected when resource availability and selections of configurations of feature extractor and classification algorithms vary. The evaluation also shows that increasing QoS requirements can be met by allocating additional CPUs for parallel processing, with only minor overhead.

A low-voltage low-power Frequency-to-voltage converter for VCO feedback linearization

A Frequency-to-voltage converter (FVC) for use in a system for feedback linearization of VCOs is presented. The VCO linearization is intended for use in an ADC application where high resolution, low power consumption, and low voltage operation is required. These requirements places stringent demands on the performance of the FVC. The proposed implementation of the FVC is a good fit for digital CMOS technology, and the system is tunable across PVT corners. Results from transistor level simulations using a 90 nm CMOS process are presented, showing a signal-to-noise and distortion ratio (SINAD) of 76.43 dB while consuming 77.6 µW from a 1.2 V supply.

Suppression of delta-sigma DAC quantisation noise by bandwidth adaptation

In this paper we present a system for adapting the bandwidth of a ΔΣ DAC based on the spectral contents of the input signal. By dynamically adjusting the bandwidth of the converter based on the transitory requirements of the input signal, quantisation noise can be suppressed further in frequency bands that are idle. It is shown how a compression scheme can be exploited to efficiently obtain the spectral information needed. A simulation model of the system is used to quantify the performance gain experimentally. The results obtained from the simulations substantiate the claim of a performance increase that outweighs the complexity incurred by the approach for certain classes of input signals.

7.7 A 118mW 23.3GS/s dual-band 7.3GHz and 8.7GHz impulse-based direct RF sampling radar SoC in 55nm CMOS

Radar sensors find use in a wide range of applications [1–4]. Impulse radars operating below 10GHz offer opportunities in applications including non-contact vital signs monitoring, such as breathing and heart rate, presence detection, and ranging. However, the wide instantaneous bandwidth incurs a power penalty from the ADC, calling for unconventional receiver (RX) architectures [4, 5]. In practical use, the received power from narrowband interferers, such as 802.11, can be much larger than the echo from the targets, requiring an unnecessarily large RX dynamic range. In this paper we report an impulse radar SoC (shown in Fig. 7.7.1), featuring a transmitter (TX) that complies with regulations for unlicensed operation, 1b direct RF sampling, and RF interference rejection. The system is self-contained, including power management and clock generation functions, and requires only an external crystal and antennas to operate.

Noise and linearity analysis of a frequency to voltage converter

In this paper we explore the noise and linearity limitations of a delay line based frequency to voltage converter (FVC) for use in an analog to digital converter (ADC) linearization system. Phase noise due to the delay line is the main source of noise in the FVC. In this paper we derive the relationship between the phase noise and the output voltage noise of the FVC. Furthermore, we characterize the constraints on the design of the delay line to ensure good linearity and derive a relationship between the series resistance of the buffer driving the output filter and the total harmonic distortion (THD). Simulation results obtained using a commercially available 90 nm process design kit (PDK) show good agreement between the predicted noise and linearity and the simulated results.

Towards a Second Order FDSM Analog-to-Digital Converter for Wireless Sensor Network Nodes

In this paper we report on implementation considerations for second order FDSM analog-to-digital converters to be used in wireless sensor network nodes. A comprehensive Verilog-A simulation model is presented along with a new control logic. The allowed increase in power compared to first order converters is presented. Simulated results demonstrate the feasibility of a second order FDSM converter, and shows that 16 times increase in power compared to a first order FDSM converter is tolerated, while still maintaining the figure-of-merit.

A VCO linearization system for ADC applications

Time-domain ADCs are increasing in popularity due in part to compatibility with deep sub-micron (DSM) CMOS technology. The performance of time-domain ADCs that use VCOs in open loop is to a large extent limited by the linearity of the output frequency of the VCO as a function of its control voltage. In this paper, we present an analysis of a system for VCO linearization, suppressing distortion and phase noise introduced by the VCO. We connect the noise from each component of the system to the performance of the ADC. Further, we demonstrate the feasibility of the system with transistor level simulations. We designed the simulated system for 12 bit linearity and simulated the transistor level model using a commercially available 90 nm CMOS process design kit (PDK).