Jorgen Christiansen

An integrated high resolution CMOS timing generator based on an array of delay locked loops

This paper describes the architecture and performance of a new high resolution timing generator used as a building block for Time to Digital Converters (TDC) and clock alignment functions. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with sub-gate delay resolution to be implemented in a standard digital CMOS process. The proposed timing generator has been mapped into a 1.0 ¿m CMOS process and a RMS error of the time taps of 48 ps has been measured with a bin size of 150 ps. Used as a TDC device a RMS error of 76 ps has been obtained.

A high-resolution time interpolator based on a delay locked loop and an RC delay line

An architecture for a time interpolation circuit with an rms error of /spl sim/25 ps has been developed in a 0.7-/spl mu/m CMOS technology. It is based on a delay locked loop (DLL) driven by a 160-MHz reference clock and a passive RC delay line controlled by an autocalibration circuit. Start-up calibration of the RC delay line is performed using code density tests (CDT). The very small temperature/voltage dependence of R and C parameters and the self calibrating DLL results in a low-power, high-resolution time interpolation circuit in a standard digital CMOS technology.

A fine time-resolution (≪ 3 ps-rms) time-to-digital converter for highly integrated designs

A multi-channel 3-ps-rms single-shot precision timeto-digital converter (TDC) is presented. The time interpolation is based on a delay-locked-loop (DLL) employing resistive interpolation to achieve least-significant-bit (LSB) sizes as small as 5 ps. To calibrate out device mismatches, only the timing-reference signals need to be calibrated. The usual need for calibrating each channel individually is avoided. After calibration, the measured differential-non-linearity (DNL) and integral-non-linearity (INL) are ±0.9 LSB and ±1.3 LSB respectively. A prototype, implemented in a commercial 130 nm technology, consumes between 34mW to 42 mW/channel and shows a voltage sensitivity of -0.19 ps/mV and a temperature dependence of 0.44 ps/°C. To the best of our knowledge this is the first time a TDC demonstrates single-shot precisions on multiple channels smaller than 3ps-rms.

Picosecond Stopwatches: The Evolution of Time-to-Digital Converters

The measurement of time intervals with high resolution, precision, and stability on a large number of channels has been used in a multitude of large-scale scientific experiments in particle and nuclear physics. In the early 1950s, however, no standard instruments were available to measure time intervals with subnanosecond time resolution for such scientific experiments. The novel Vernier chronotron proposed in the 1950s by Emilio Gatti [1], based on two oscillators at slightly different frequencies, was an important step toward future detectors and instrumentation able to access high-resolution time measurements in the ps domain. During the 1960s and 1970s, further novel time-to-digital converter (TDC) architectures were developed, and several of these were used until the 1980s in standard modular instrumentation modules, including those based on the Nuclear Instrumentation Module (NIM), Computer Automated Measurement and Control (CAMAC), IEEE Fastbus, and Versa Module Eurocard (VME) standards. At the end of the 1980s, the required number of TDC channels in high energy physics (HEP) experiments increased rapidly, reaching the tens <?Pub Caret?>and hundreds of thousands of measurement channels. This gave rise to the development of various fully integrated, multichannel TDC application specified integrated circuits (ASICs) for use in HEP [2], [3].

Performance evaluation of digital pixel readout chip architecture operating at very high rate through a reusable UVM simulation framework

A large scale demonstrator pixel readout chip is currently being designed by the RD53 Collaboration, with the goal of proving the suitability of 65 nm technology for the extreme operating conditions associated to the High Luminosity upgrades of the ATLAS and CMS experiments at the Large Hadron Collider. The VEPIX53 simulation and verification environment was developed in order to support the chip design flow at different steps, from architectural modeling and optimization to final design verification, thanks to the flexibility and reusability of System Verilog and the Universal Verification Methodology (UVM) library. In this work a test case of VEPIX53 is presented where an existing digital pixel architecture, already implemented in a small scale prototype chip, is simulated for evaluating whether it satisfies the specifications of the large scale demonstrator chip. The architecture inefficiency was measured by the analysis components of the environment, with respect to different models of analog front-ends and different pixel hit memory sizes, showing possible solutions for optimization.

A single-event upset robust, 2.2 GHz to 3.2 GHz, 345 fs jitter PLL with triple-modular redundant phase detector in 65 nm CMOS

This paper presents a Single Event Upset (SEU) robust low phase-noise PLL for clock generation in harsh environments like nuclear and space applications. The PLL has been implemented in a 65 nm CMOS technology. A low noise LC-tank oscillator is included with a tuning range from 2.2 GHz to 3.2 GHz. The PLL includes a new phase detector and divider with Triple Modular Redundancy (TMR) to suppress Single Event Effects in ionizing radiation environments. A highly reconfigurable bandwidth from 0.7 MHz to 2 MHz provides optimal reference phase noise filtering. The PLL has been designed and measured to operate in a temperature range from −25 C to 125 C and features a jitter of 345 fs rms with a power consumption of 11.7 mW and is tolerant to 10 % supply variations. Single Event Upset laser tests are performed to verify the triplicated circuit performance.

Serial powering optimization for CMS and ATLAS pixel detectors within RD53 collaboration for HL-LHC: System Level Simulations and Testing

Serial powering is the baseline choice for low mass power distribution for the CMS and ATLAS HL-LHC pixel detectors. Two 2.0 A Shunt-LDO regulators are integrated in a prototype pixel chip implemented in 65-nm CMOS technology and used to provide constant supply voltages to its power domains from a constant input current. Performance results from testing prototype Shunt-LDO regulators are shown, including their behaviour after x-ray irradiation. The system level simulation studies, which had been performed with a detailed regulator design in a serially powered topology, have been validated.

Low-power optimisation of a pixel array architecture for next generation High Energy Physics detectors

A large scale pixel readout chip is being designed by the RD53 Collaboration, in order to prove the suitability of 65 nm technology for the extreme operating conditions foreseen for the High Luminosity upgrades of the ATLAS and CMS experiments at CERN. The use of advanced digital design and simulation tools is essential to guide architectural and implementation choices for the design and optimisation of pixel chips which will be powered from a serial powering scheme. In this work, low power design techniques are reviewed and critically selected based on the requirements of the target application. Chosen techniques are adopted and results of the low power optimisation are presented for a basic unit of the system.

A SystemVerilog-UVM Methodology for the Design, Simulation and Verification of Complex Readout Chips in High Energy Physics Applications

The adoption of a system-level simulation environment based on standard methodologies is a valuable solution to handle system complexity and achieve best design optimization. This work is focused on the implementation of such a platform for High Energy Physics (HEP) applications, i.e. for next generation pixel detector readout chips in the framework of the RD53 collaboration. The generic and re-usable environment is capable of verifying different designs in an automated fashion under a wide and flexible stimuli space; it can also be used at different stages of the design process, from initial architecture optimization to final design verification.

Fine-Time Resolution Measurements for High Energy Physics Experiments

Fine-time resolution measurements are attracting increasing attention in the high-energy-physics (HEP) community, where a large number of measurement channels must often be realized with a single ASIC. In this contribution, a multi-channel time-to-digital converter (TDC) architecture with a delay-locked-loop (DLL) in its first stage and a resistive interpolation scheme in its second stage is presented. The size of the TDC’s least-significant-bit (LSB) is controlled by a reference clock and so can be continuously adjusted from 5 to 20 ps. A global calibration scheme that avoids the need to calibrate each channel separately is also used. Critical design aspects like device mismatch, supply noise sensitivity and process-voltage and temperature (PVT) variation are discussed. When realized in a 130 nm technology, the prototype ASIC achieved a single-shot resolution of better than 2.5 ps-rms. The measured integral-non-linearity (INL) and differential-non-linearity (DNL) were found to be ±1.4 LSB and ±0.9 LSB respectively.