A. Marchioro

Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: practical design aspects

We discuss design issues related to the extensive use of Enclosed Layout Transistors (ELTs) and guard rings in deep submicron CMOS technologies in order to improve radiation tolerance of ASICs designed for the LHC experiments (the Large Hadron Collider at present under construction at CERN). We present novel aspects related to the use of ELTs: noise measured before and after irradiation up to 100 Mrad (SiO/sub 2/), a model to calculate the W/L ratio and matching properties of these devices. Some conclusions concerning the density and the speed of ICs conceived with this design approach are finally drawn.

An integrated 16-channel CMOS time to digital converter

An integrated 16-channel Time to Digital Converter (TDC) for use in the NA48 experiment at CERN has been developed in a 1 /spl mu/m CMOS technology. The resolution is 156ns and the total time history is 204.8 ms. Buffering of up to 128 hits is done in on-chip FIFOs. The chip area is 25 mm/sup 2/. The vernier circuit consists of a 16-tap voltage-controlled delay chain controlled by a Delay Locked Loop (DLL). Read out is possible at 40 MHz. JTAG/IEEE 1149.1 protocol has been incorporated to allow in-site testing of the chip. The JTAG data path is also used to access internal control and status registers. >

A radiation tolerant gigabit serializer for LHC data transmission

In the future LHC experiments, some data acquisition and trigger links will be based on Gbit/s optical fiber networks. In this paper, a configurable radiation tolerant Gbit/s serializer (GOL) is presented that addresses the high-energy physics experiments requirements. The device can operate in four different modes that are a combination of two transmission protocols and two data rates (0.8 Gbit/s and 1.6 Gbit/s). The ASIC may be used as the transmitter in optical links that, otherwise, use only commercial components. The data encoding schemes supported are the CIMT (G-Link) and the 8B/10B (Gbit-Ethernet & Fiber Channel). To guarantee robustness against total dose irradiation effects over the lifetime of the experiments, the IC was fabricated in a standard 0.25 μm CMOS technology employing radiation tolerant layout practices.

Single event effects in static and dynamic registers in a 0.25 /spl mu/m CMOS technology

We have studied single event effects in static and dynamic registers designed in a quarter micron CMOS process. In our design, we systematically used guardrings and enclosed (edgeless) transistor geometry to improve the total dose tolerance. This design technique improved both the SEL and SEU sensitivity of the circuits. Using SPICE simulations, the measured smooth transition of the cross-section curve between LET threshold and saturation has been traced to the presence of four different upset modes, each corresponding to a different critical charge and sensitive area. A new architecture to protect the content of storage cells has been developed, and a threshold LET around 89 MeV cm/sup 2/ mg/sup -1/ has been measured for this cell at a power supply voltage of 2 V.

G-link and gigabit Ethernet compliant serializer for LHC data transmission

Gbit/s data transmission links will be used in several LHC detectors in trigger and data acquisition systems. In these experiments, the transmitters will be subject to high radiation doses over the lifetime of the experiments. In this work, a radiation tolerant transmitter ASIC is described. The IC supports two standard protocols, the G-link and the Gbit-Ethernet, and sustains transmission of data at both 800 Mbit/s and 1.6 Gbit/s. The ASIC was implemented in a mainstream 0.25 /spl mu/m CMOS technology employing radiation tolerant layout practices. A 1.2 Gbit/s prototype with reduced functionality was tested. The ASIC behavior under total dose irradiation as well as its susceptibility to single event upsets was studied and the results are reported here.

The GBT-SerDes ASIC prototype

In the framework of the GigaBit Transceiver project (GBT), a prototype, the GBT- SerDes ASIC, was developed, fabricated and tested. To sustain high radiation doses while oper- ating at 4.8Gb/s, the ASIC was fabricated in a commercial 130 nm CMOS technology employing radiation tolerant techniques and circuits. The transceiver serializes-deserializes the data, Reed- Solomon encodes and decodes the data and scrambles and descrambles the data for transmission over optical fibre links. This paper describes the GBT-SerDes architecture, and presents the test results.

Deep submicron CMOS technologies for the LHC experiments

Abstract The harsh radiation environment at the Large Hadron Collider (LHC) requires radiation hard ASICs. This paper presents how a high tolerance for total ionizing dose can be obtained in commercial deep submicron technologies by using enclosed NMOS devices and guard rings. The method is explained, demonstrated on transistor and circuit level, and design implications are discussed. A model for the effective W/L of an enclosed transistor is given, a radiation-tolerant standard cell library is presented, and single event effects are discussed.

Receiver ASIC for timing, trigger and control distribution in LHC experiments

An ASIC receiver has been developed for the optical timing, trigger and control distribution system for LHC detectors. It is capable of recovering the LHC reference clock and the first-level trigger decisions and make them available to the front-end electronics properly deskewed in time. The timing receiver is also capable of recognising individually addressed commands to provide some slow control capability. Its main functions include post-amplification of the signal received from a PINFET preamplifier, automatic gain control, data/clock separation, demultiplexing of the trigger and data channels and programmable coarse/fine deskewing functions. The design has been mapped into a standard 1 /spl mu/m CMOS process with all the analogue and timing critical functions implemented in full custom. The jitter measured on the recovered clock is less than 100 ps for input optical powers down to -25 dBm. The time deskewing functions allow to phase shift the system clock and the first level trigger accept signal up to a maximum of sixteen clock cycles in steps of 0.1 ns.

Characterization of a commercial 65 nm CMOS technology for SLHC applications

The radiation characteristics with respect to Total Ionizing Dose (TID) and Single-Event Upsets (SEUs) of a 65 nm CMOS technology have been investigated. Single transistor structures of a variety of dimensions and several basic circuits were designed and fabricated. The circuits include a 64-kbit shift-register, a 56-kbit SRAM and a ring-oscillator. The test chips were irradiated up to 200 Mrad with an X-ray beam and the corresponding transistor threshold shifts and leakage currents were measured. Heavy-ion beam irradiation was performed to assess the SEU sensitivity of the digital parts. Overall, our results give the confidence that the chosen 65 nm CMOS technology can be used in future High Energy Physics (HEP) experiments even without Hardness-By-Design (HBD) solutions, provided that constant monitoring of the TID response is carried out during the full manufacturing phase of the circuits.

Experimental search for neutron-antineutron transitions with free neutrons

Abstract The observation of neutron-antineutron transitions would be direct evidence for baryon number violation. For the first time an experiment has been carried out to search for this phenomenon with neutrons in free flight. The experiment using the research reactor at the Institut Laue-Langevin in Grenoble has set a lower limit to the oscillation time τ n n of 106 s.