Joris Lambrecht

Design and Experimental Verification of a Transimpedance Amplifier for 64-Gb/s PAM-4 Optical Links

The use of four-level pulse-amplitude modulation (PAM-4) has emerged as a solution to increase the serial rate in short-range optical links, offering twice the data throughput but requiring similar bandwidth as on–off keying. However, the receiver design should take into account the increased susceptibility of PAM-4 to noise, intersymbol interference, and nonlinearity. This papers explores these challenges, and details the design of a transimpedance amplifier (TIA) for 64-Gb/s PAM-4 optical links. The TIA was implemented in 0.13-µm SiGe BiCMOS, and has a power consumption of 180xa0xa0mW. It contains a digital gain controller, which allows switching between four gain modes, to tradeoff sensitivity against linearity. Bit error rate (BER) measurements show that the dynamic range is significantly extended: Optical modulation amplitudes between <inline-formula><tex-math notation=LaTeX>

A DC-coupled 50 Gb/s 0.064 pJ/bit thin-oxide level shifter in 28 nm FDSOI CMOS

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Resonant optical receiver design by series inductive peaking for sub-6 GHz RoF

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100 Gb/s DAC-less and DSP-free Transmitters using GeSi EAMs for Short-Reach Optical Interconnects

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EOCB-Platform for Integrated Photonic Chips Direct-on-Board Assembly within Tb/s Applications

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DAC-Less and DSP-Free 112 Gb/s PAM-4 Transmitter Using Two Parallel Electroabsorption Modulators

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Real-Time and DSP-free 128 Gb/s PAM-4 Link using a Binary Driven Silicon Photonic Transmitter

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Aerosol-Jet Printed Interconnects for 60 Gb/s CMOS Driver and Microring Modulator Transmitter Assembly

High-speed optical interconnects require compact, low-power driver electronics for optical modulators. Inverter based CMOS driver circuits show very low power consumption. However, the output swing is typically limited to the supply voltage which is typically insufficient for optical modulators, requiring a cascoded output driver and level shifter. In this work, we present a new DC-coupled thin-oxide level shifter topology in a 28 nm FDSOI CMOS technology enabling data rates up to 50 Gb/s with a power efficiency of 0.064 pJ/bit.