Jorma Skyttä

On Parallelization of High-Speed Processors for Elliptic Curve Cryptography

This paper discusses parallelization of elliptic curve cryptography hardware accelerators using elliptic curves over binary fields F2m. Elliptic curve point multiplication, which is the operation used in every elliptic curve cryptosystem, is hierarchical in nature, and parallelism can be utilized in different hierarchy levels as shown in many publications. However, a comprehensive analysis on the effects of parallelization has not been previously presented. This paper provides tools for evaluating the use of parallelism and shows where it should be used in order to maximize efficiency. Special attention is given for a family of curves called Koblitz curves because they offer very efficient point multiplication. A new method where the latency of point multiplication is reduced with parallel field arithmetic processors is introduced. It is shown to outperform the previously presented multiple field multiplier techniques in the cases of Koblitz curves and generic curves with fixed base points. A highly efficient general elliptic curve cryptography processor architecture is presented and analyzed. Based on this architecture and analysis on the effects of parallelization, a few designs are implemented on an Altera Stratix II field-programmable gate array (FPGA).

High-Speed Elliptic Curve Cryptography Accelerator for Koblitz Curves

We present an FPGA-based accelerator for elliptic curve cryptography on a Koblitz curve targeting for applications requiring very high speed. The accelerator supports fast computation of point multiplication by using window methods as well as multiple point multiplications with joint sparse form representations. Optimized operation-specific processing units are used in order to improve performance. Throughput is increased by pipelining operations. The accelerator was implemented in an Altera Stratix II FPGA and it computes point multiplication on average in 16.36 ¿s and achieves a maximum of 161,290 operations per second. A 3-term multiple point multiplication requires 35.06 ¿s with a maximum of 60,603 operations in second.

Wearable authentication device for transparent login in nomadic applications environment

This paper describes a wearable authentication device for continuous user authentication and transparent login procedure in nomadic applications environment, where users are mobile and current authentication methods are not applicable. The wearable authentication device is a wristband in which the user authentication is done by using the fingerprint and to ensure that the person is wearing the device, it measures continuously his vital signs (skin temperature and heart rate) along with body capacitance and acceleration. By wearing the authentication device, the user can login transparently to any computer simply by approaching it. The prototype of the wearable authentication device was implemented and demonstrated successfully. The user was authenticated with the fingerprint and his presence could be verified continuously by using the skin temperature and the body capacitance. In addition, the heart rate of the user could be obtained from the pulse oximeter output. The received signal strength of the wireless connection offered an inexpensive and simple way to implement the transparent login by estimating the range between the user and a terminal.

Dijkstra's Shortest Path Routing Algorithm in Reconfigurable Hardware

This paper discusses the suitability of reconfigurable computing architectures to different network routing methods. As an example of the speedup offered by reconfigurable logic, the implementation of Dijkstras shortest path routing algorithm is presented and its performance is compared to a microprocessor-based solution.

FPGA Design of Self-certified Signature Verification on Koblitz Curves

Elliptic curve signature schemes offer shorter signatures compared to other methods and a family of curves called Koblitz curves can be used for reducing the cost of signing and verification. This paper presents an FPGA implementation designed specifically for rapid verification of self-certified identity based signatures using Koblitz curves. Verification requires computation of three elliptic curve point multiplications which are computed efficiently with 3-term multiple point multiplication and joint sparse form. Certain improvements to precomputations associated with multiple point multiplications are introduced. It is shown that, when using parallel processors, it is possible to gain considerable increases in the number of operations per second by allowing slightly longer computation times for single operations. It is demonstrated that up to 166,000 verifications per second can be computed using a single Altera Stratix II FPGA.

Bridging the gap between future software and hardware engineers: a case study using the Nios softcore processor

As digital designs grow both in size and functionality, the importance of software development concepts has increased. This has led to a demand in the industry for engineers with good skills in both electrical engineering and computer science. However, the general trend in undergraduate education has been a divergence of these two historically close fields of study. To have an influence in the opposite direction, a digital laboratory course was reformed at the Helsinki University of Technology. The modernized laboratory course includes exercises on Alteras Nios development platform, which has been enhanced with a custom-designed expansion board. The exercises include both software and hardware concepts and contribute to a better understanding between future electrical engineers and computer scientists. Based on student feedback, the initial objective of bridging the gap between software and hardware engineers has been achieved.

How small and still effective a CMOS-SoC could ever be?

In this paper, effects of expected physical limits of CMOS technology on the performance of small-scale System-on-Chips (SoCs) are described. The exponential progress of CMOS technology has entered to the saturation phase. This could be called, if we like, a third phase of the Moores law. In this third phase of development, the peak-performance of SoCs is not any more in the main concern. Instead of that, we could see an explosion of creative small-size applications: bionic appendages, smartphones with smart sensors, networks of tiny sensors, and a host of other applications we have yet to imagine. The International Technology Roadmap for Semiconductors (ITRS) lists expected performance parameters for CMOS technology up to the year 2028. In this paper, it is shown that starting from the simple RTL architecture parameters, e.g., gate count, and using performance figures taken from ITRS, we are able to figure out the (space-time-energy) performance limits of CMOS implementation of any logic architecture. As a practical example, the study of performance limits of a novel digital receiver suitable to be used in different capillary networks of Internet-of-Things applications is described, here. Design space exploration technique described in this paper can be used to find out performance limits of wide range of smart object applications.

A VHDL Generator for Elliptic Curve Cryptography

A VHDL generator called SIG-ECPM is presented in this paper. SIG-ECPM generates fully synthesizable and portable VHDL code implementing an elliptic curve point multiplication, which is the basic operation of every elliptic curve cryptosystem. The use of automated design flow significantly shortens design times and reduces error proneness.

IPv6 over ATM flow-handling

This paper explores the ways to obtain high capacity allocation in the backbone network. IPv6 offers new possibilities for IP over ATM signalling.

A new wireless paging network architecture

Paging is a one-way telecommunication service providing the means to send an alert signal or a short message to a pager. Traditional wide-area paging systems are mainly based on wired data transfer from paging area controllers to the base stations. In this paper we present a novel method to implement paging networks. Conventional paging networks use normally leased land lines to send pages from the paging network controller to the base stations located all over the country. In many cases the cost of those land lines is prohibitive, and therefore alternatives must be found. The new paging architecture proposed in this paper consists of a satellite channel and of a packet radio channel. Both channels are unidirectional. Together these channels provide a bi-directional communication channel. A cost-effective solution is to use a time-divided part of the paging channel for the packet radio. This can be done only if the packet radio does not decrease too much the paging capacity. To enable high paging capacity the packet radio network has to be efficiently routed.