José Carlos Alves

FASt - an autonomous sailing platform for oceanographic missions

Sailing has been for long times the only means of ship propulsion at sea. Although the performance of a sailing vessel is well below the present power driven ships, either in terms of navigation speed and predictability, wind energy is absolutely renewable, clean and free. Unmanned autonomous sailing boats may exhibit a virtually unlimited autonomy and be able to perform unassisted missions at sea for long periods of time. Promising applications include oceanographic and weather data collecting, surveillance and even military applications. The Microtransat competition, launched in Europe in 2006, has been a key initiative to promote the development of robotic unmanned sailing boats. Various regattas have taken place across Europe and the ultimate challenge will be a transatlantic race. This paper presents an autonomous sailing boat developed at the University of Porto, Portugal, with emphasis on the hardware and software computing infrastructure. This platform is capable of carrying a few kilograms of sensing equipment that can be hooked to the boats main computer, also providing support for short and long range data communications.

Autonomous sailboats: An emerging technology for ocean sampling and surveillance

Autonomous sailboats are robotic vessels that use wind energy for propulsion and control the sails and rudders without human intervention. The use of autonomous sailboats for ocean sampling has been tentatively proposed before, but there have been minor efforts towards the development and deployment of actual prototypes, due to a number of technical limitations and significant risks of operation. Currently, most of the limitations have been surpassed, with the availability of extremely low power electronics, flexible computational systems, reliable communication devices and high performance renewable power sources. At the same time, some of the major risks have been mitigated, allowing this emerging technology to become an effective tool for a wide range of applications in real scenarios. We illustrate some of these scenarios and we describe the status of the current efforts being made to develop operational prototypes.

Auto-heading controller for an autonomous sailboat

This paper addresses the design and implementation of feedback controllers for the direction of autonomous robotic sailboats. In order to design such a controller, it is important to determine a model for the sailboat dynamics during turns. However, there are many uncontrollable factors that may affect the direction of the sailboat, which make it difficult to obtain an accurate model and require a lot of sensors to feed a proper controller. Instead, we assume a rather simple model relating the most important variables and concentrate on data that can easily be available with simple low-cost sensors, compensating the lack of accuracy of the model with the robustness of the controller. We describe our approach to extract the parameters of such a dynamic model using data obtained in field experiments and we show how to use this model to tune a PI controller. As a case study, we use the FASt vehicle, a 2.5 m long robotic sailing boat capable of fully autonomous navigation through a set of predefined marks. Experimental results show the performance of the designed controller.

A scalable array for Cellular Genetic Algorithms: TSP as case study

Cellular Genetic Algorithms (cGAs) exhibit a natural parallelism that makes them interesting candidates for hardware implementation, as several processing elements can operate simultaneously on subpopulations shared among them. This paper presents a scalable architecture for a cGA, suitable for FPGA implementation. A regular array of custom designed processing elements (PEs) works on a population of solutions that is spread into dual-port memory blocks locally shared by adjacent PEs. A travelling salesman problem with 150 cities was used to verify the implementation of the proposed cGA on a Virtex-6 FPGA, using a population of 128 solutions with different levels of parallelism (1, 4, 16 and 64 PEs). Results have shown that an increase of the number of PEs does not degrade the quality of the convergence of the iterative process, and that the throughput increases almost linearly with the number of PEs. Comparing with a software implementation running in a PC, the cGA with 64 PEs has shown a 45x speedup.

REFLECT: Rendering FPGAs to Multi-core Embedded Computing

The relentless increase in capacity of Field-Programmable Gate-Arrays (FPGAs) has made them vehicles of choice for both prototypes and final products requiring on-chip multi-core, heterogeneous and reconfigurable systems. Multiple cores can be embedded as hard- or soft-macros, have customizable instruction sets, multiple distributed RAMs and/or configurable interconnections. Their flexibility allows them to achieve orders of magnitude better performance than conventional computing systems via customization. Programming these systems, however, is extremely cumbersome and error-prone and as a result their true potential is only achieved very often at unreasonably high design efforts. This project covers developing, implementing and evaluating a novel compilation and synthesis system approach for FPGA-based platforms. We rely on Aspect-Oriented Specifications to convey critical domain knowledge to a mapping engine while preserving the advantages of a high-level imperative programming paradigm in early software development as well as program and application portability. We leverage Aspect-Oriented specifications and a set of transformations to generate an intermediate representation suitable to hardware mapping. A programming language, LARA, will allow the exploration of alternative architectures and design patterns enabling the generation of flexible hardware cores that can be easily incorporated into larger multi-core designs. We will evaluate the effectiveness of the proposed approach using partner-provided codes from the domain of audio processing and real-time avionics. We expect the technology developed in REFLECT to be integrated by our industrial partners, in particular by ACE, a leading compilation tool supplier for embedded systems, and by Honeywell, a worldwide solution supplier of embedded high-performance systems.

RVC-a reconfigurable coprocessor for vector processing applications

This work presents RVC (Reconfigurable Vector Coprocessor), a FPGA based custom computing machine for vector processing applications. This system was built to serve as an implementation platform for a custom vector processor designed for a digital signal processing application. Although its architecture has been in part dictated by the immediate needs of that dedicated processor, it also serves for other custom machines exhibiting similar requirements of vector processing.

A framework for hardware cellular genetic algorithms: An application to spectrum allocation in cognitive radio

The genetic algorithm (GA) is an optimization metaheuristic that relies on the evolution of a set of solutions (population) according to genetically inspired transformations. In the variant of this technique called cellular GA, the evolution is done separately for subgroups of solutions. This paper describes a hardware framework capable of efficiently supporting custom accelerators for this metaheuristic. This approach builds a regular array of problem-specific processing elements (PEs), which perform the genetic evolution, connected to shared memories holding the local subpopulations. To assist the design of the custom PEs, a methodology based on highlevel synthesis from C++ descriptions is used. The proposed architecture was applied to a spectrum allocation problem in cognitive radio networks. For an array of 5×5 PEs in a Virtex-6 FPGA, the results show a minimum speedup of 22× compared to a software version running on a PC and a speedup near 2000× over a MicroBlaze soft processor.

Specifying Compiler Strategies for FPGA-based Systems

The development of applications for high-performance Field Programmable Gate Array (FPGA) based embedded systems is a long and error-prone process. Typically, developers need to be deeply involved in all the stages of the translation and optimization of an application described in a high-level programming language to a lower-level design description to ensure the solution meets the required functionality and performance. This paper describes the use of a novel aspect-oriented hardware/software design approach for FPGA-based embedded platforms. The design-flow uses LARA, a domain-specific aspect-oriented programming language designed to capture high-level specifications of compilation and mapping strategies, including sequences of data/computation transformations and optimizations. With LARA, developers are able to guide a design-flow to partition and map an application between hardware and software components. We illustrate the use of LARA on two complex real-life applications using high-level compilation and synthesis strategies for achieving complete hardware/software implementations with speedups of 2.5× and 6.8× over software-only implementations. By allowing developers to maintain a single application source code, this approach promotes developer productivity as well as code and performance portability.

FPGA Based Engines for Genetic and Memetic Algorithms

Memetic algorithms are highly efficient procedures to solve complex optimization problems. They combine strengths of well known metaheuristics, like the genetic algorithm (GA), with local search (LS) procedures to intensify the search. This paper proposes a computing architecture to support the execution of a memetic algorithm (MA). The Travelling Salesman Problem is elected as a case study for this work since it is a representative problem in the field of graph theory. A GA implementation in a Virtex 4 FPGA device is shown for solving a TSP with 1002 cities at a frequency of 96MHz. The proposed architecture is based in a pipeline capable of processing 1 city per clock cycle. New ideas are discussed on how to implement a LS on a GA solution by exploiting the run-time reconfiguration features of modern FPGAs.

An FPGA-Based Embedded System for a Sailing Robot

This paper presents an embedded hardware/software implementation for the computing system of a small scale unmanned autonomous sailing boat. The system is integrated in a single XILINX FPGA, and hosts a Microblaze soft processor surrounded with heterogeneous, custom designed, control and processing modules than handle the interface with all the sensors, actuators and communication devices of the sailing boat. These interfacing modules implement tasks that have been decentralized from the main processor, thus alleviating its computational load and providing processing time for higher level software applications. Using an FPGA to implement an integrated single-chip computing system, as an alternative to conventional processors, has proven to be a very flexible solution as it eases the migration of computation tasks between the hardware and software domains, and more importantly, allowing the rapid adaptation of the digital interfacing hardware in order to support additional peripheral devices required for an application mission. The software component of the boats control system runs on the top of the uClinux embedded operating system and is formed by various concurrent applications developed in C with the standard Linux libraries. The remote monitoring, configuration and operation of the sailing boat is done via a WiFi link, using a graphics interactive application that runs on a conventional PC.