José Silva Matos

Control and observation of analog nodes in mixed-signal boards

BST is a well established standard and testability framework for digital ICs and boards. The paper presents a test support IC controlled by an IEEE1149.1 interface, capable of providing access to analog nodes in mixed-signal boards. The proposed architecture (ABSINT - Analog to Boundary Scan Interface) is described and relevant implementation issues are discussed. A demonstrator IC implementing the ABSINT architecture is presented, and it is shown how it can be used to provide analog test channels under control of IEEE1149.1.<<ETX>>

A boundary scan test controller for hierarchical BIST

A test controller for BIST of Boundary Scan Boards is described. It consists of a test processor core, with an optimized architecture for controlling the board-level BST infrastructure, and a system level testability bus interjace, allowing the implementation of a hierarchical test strategy. Automatic test pattern generation for this dedicated processor simplifies the task of providing a board-level BIST solution.

RVC-a reconfigurable coprocessor for vector processing applications

This work presents RVC (Reconfigurable Vector Coprocessor), a FPGA based custom computing machine for vector processing applications. This system was built to serve as an implementation platform for a custom vector processor designed for a digital signal processing application. Although its architecture has been in part dictated by the immediate needs of that dedicated processor, it also serves for other custom machines exhibiting similar requirements of vector processing.

Boundary scan test, test methodology, and fault modeling

The test technique called “boundary scan test” (BST) offers new opportunities in testing but confronts users with new problems too. The implementation of BST in a chip has become an IEEE standard and users on board level are the next group to begin thinking about using the new possibilities. This article addresses some of the questions about changes in board-level testing and fault diagnosis. The fault model itself is also affected by using BST. Trivial items are extended with more sophisticated details in order to complete the fault model. Finally, BST appears to be a test technique that offers a high degree of detectability on board level, but for diagnosis, some additional effort has to be made.

Architecture of test support ICs for mixed-signal testing

Discusses the need of a test infrastructure to support the testing of mixed-signal electronic systems, and discusses a general architecture for test support ICs that can be used to build it. An implementation of a subset of this architecture is described together with its application in a practical example.<<ETX>>

An efficient computational scheme for robot manipulators

A novel robot manipulator computational scheme that is a blend of ordinary and Boolean algebra is presented. This method may also be interpreted as a dedicated compiler that optimizes the online computing time at the expense of the offline stage. The offline requirements are alleviated by the implementation of some general rules that stem from the structure of the robot manipulator equations, and the online computing time is optimized through the use of binary decision diagrams. The algorithm is illustrated on the example of a 2R robot manipulator. The results show a considerable computational improvement over conventional sequential machines, and they clearly point out new computational parallel architectures. It is observed that the proposed algorithm is not restricted to robot dynamic computations, but is also applicable to many other computing structures.<<ETX>>

FAFNER-accelerating nesting problems with FPGAs

The nesting problem consists of defining the cutting plan of a piece of raw material in smaller irregular shapes, and has applications in the apparel and footwear industries. Due to its NP-hard nature, the optimal solution can only be guaranteed by exhaustively trying all possible solutions and choosing the best one. Because this is impractical in real-life industrial problems, automatic approaches are based on optimization meta-heuristics that search for sub-optimal but good enough solutions. These optimization techniques rely on the construction and evaluation of several solutions, thus requiring heavy geometric manipulation of the irregular polygons that constitute the problem data. Efficient processing of this geometric information is thus necessary to make effective fully automatic approaches to nesting problems in industrial environments. This paper describes FAFNER, an FPGA-based custom computing machine that is used to accelerate the geometric operations, that are in the core of heuristic solutions to the nesting problem. The system is used as an auxiliary processor attached to a low cost personal computer, and combines a custom programmable processor with an array of custom circuits for the processing of irregular polygons.

Flexible hardware acceleration for nesting problems

The nesting (or placement) problem is an NP-hard combinatorial problem with important industrial applications, e.g. in apparel or footwear industry. This paper describes a hardware infrastructure to accelerate the processing of the underlying geometric information. The system consists of an FPGA-based reconfigurable platform enhanced by an ASIC for the processing of irregular polygons. The paper discusses the need for such a platform, establishes the main design guidelines and describes the architecture and modes of operation of both the reconfigurable infrastructure and the dedicated IC.

A vector architecture for higher-order moments estimation

Higher-order statistics extend the analysis methods of non-linear systems and non-Gaussian signals based on the autocorrelation and power spectrum. The main drawback of their use in real time applications is the high complexity of their estimation due to the large number of arithmetic operations. This paper presents an experimental vector architecture for the estimation of the higher-order moments. The processors core is a pipelined multiply-accumulate unit that receives four data vectors and computes in parallel the moment taps up to the fourth-order. The design of custom cache memory organization and address generation circuits has led to more than 11 operations per clock cycle. The architecture was modeled and simulated in Verilog and is presently being implemented in XILINX field-programmable gate arrays (FPGAs) and one custom integrated circuit for the multiply-accumulate unit.

ADC testing using joint time—frequency analysis

Abstract Analog-to-digital converter (ADC) characterization is usually performed using stationary stimuli like sine waves. However, the use of a non-stationary stimulus, besides providing testing conditions closer to those found in real applications, can lead to interesting improvements in ADC testing speed. This kind of signal needs proper processing techniques in order to extract useful information. In this paper we propose the use of joint time–frequency analysis (JTFA) for this purpose. The basic principles of the technique, and how it can be used in ADC testing are presented. In particular, a method for characterising an ADC on its entire bandwidth using a single stimulus is described.