José Luis Briz
University of Zaragoza
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Featured researches published by José Luis Briz.
applications and theory of petri nets | 1994
José Luis Briz; José Manuel Colom
Petri Nets should be implemented in an efficient and reliable way, specially when they are going to be used for critical problems, like that of giving support to Discrete Event Systems Simulation, whichever sequential or parallel strategies are adopted. One of the critical points while implementing a Petri Net, is that of determining whether a transition is enabled. In this contribution we classify transitions in several classes. The enabling of a transition is characterized by means of a Linear Enabling Function (LEF), that depends on the class. For some classes a transformation must be applied, preserving the behavior of the net. We show how LEFs can be applied to build a Simulation Engine that uses as data structure a DES described in terms of a Timed Petri Net, taking benefit of the properties of LEFs.
international conference on supercomputing | 1998
Pablo Ibáñez; Víctor Viñals; José Luis Briz; María Jesús Garzarán
A common mechamsm to pcrlorm hat-dware-based pl-efetching for regular accesses to arrays and chained lists is based on a Load/Store cache (LSC). An LSC associates the address of a Id/SC instruction with Its individual hchavior at every entry. WC show that the implementation cost of the LSC is rather high, and that using it is Ineff’icicnt. We aim to decrease the cost of the LSC but not its pcrl’ormancc. This may he done preventing useless instructions from hemg stored in the LSC. We propose eliminatmg those inslructions that never miss, and those that follow a sequential pilttWl1. This may be carried out by insertin, 0 a lci/ it inslruction in the 1,SC whenever it misses in the data cache (on-miss insertion), and issuing sequential prefetching simultaneously. After having analy~d the perf’ormancc of this proposal through a cycle-by-cycle simulation oveta set 01. 25 benchmarks selected from SPEC9.5, SPEC92 and Perfect Club, we conclude that an LSC of only 8 entries, which combines on-miss insertion and sequential prettching, performs hetter than a conventional LSC of 5 I2 entries. We think thal the low COSI of the proposal makes it worth being taken into account for the development of future microprocessors.
ACM Sigarch Computer Architecture News | 2006
Luis Ramos; José Luis Briz; Pablo Ibáñez; Víctor Viñals
In this paper we evaluate four hardware data prefetchers in the context of a high-performance three-level on chip cache hierarchy with high bandwidth and capacity. We consider two classic prefetchers (Sequential Tagged and Stride) and two correlating prefetchers: PC/DC, a recent method with a superior score and low-sized tables, and P-DFCM, a new method. Like PC/DC, P-DFCM focuses on local delta sequences, but it is based on the DFCM value predictor. We explore different prefetch degrees and distances. Running SPEC2000, Olden and IAbench applications, results show that this kind of cache hierarchy turns prefetching aggressiveness into success for the four prefetchers. Sequential Tagged is the best, and deserves further attention to cut it losses in some applications. PC/DC results are matched or even improved by P-DFCM, using far fewer accesses to tables while keeping sizes low.
international symposium on low power electronics and design | 2013
Alamelu Sankaranarayanan; Ehsan K. Ardestani; José Luis Briz; Jose Renau
With progressive generations and the ever-increasing promise of computing power, GPGPUs have been quickly growing in size, and at the same time, energy consumption has become a major bottleneck for them. The first level data cache and the scratchpad memory are critical to the performance of a GPGPU, but they are extremely energy inefficient due to the large number of cores they need to serve. This problem could be mitigated by introducing a cache higher up in hierarchy that services fewer cores, but this introduces cache coherency issues that may become very significant, especially for a GPGPU with hundreds of thousands of in-flight threads. In this paper, we propose adding incoherent tinyCaches between each lane in an SM, and the first level data cache that is currently shared by all the lanes in an SM. In a normal multiprocessor, this would require hardware cache coherence between all the SM lanes capable of handling hundreds of thousands of threads. Our incoherent tinyCache architecture exploits certain unique features of the CUDA/OpenCL programming model to avoid complex coherence schemes. This tinyCache is able to filter out 62% of memory requests that would otherwise need to be serviced by the DL1G, and almost 81% of scratchpad memory requests, allowing us to achieve a 37% energy reduction in the on-chip memory hierarchy. We evaluate the tinyCache for different memory patterns and show that it is beneficial in most cases.
ACM Transactions on Architecture and Code Optimization | 2016
Ehsan K. Ardestani; Rafael Trapani Possignolo; José Luis Briz; Jose Renau
Five percent to 25% of power could be wasted before it is delivered to the computational resources on a die, due to inefficiencies of voltage regulators and resistive loss. The power delivery could benefit if, at the same power, the delivered voltage increases and the current decreases. This article presents CoreUnfolding, a technique that leverages voltage Stacking to improve power delivery efficiency. Our experiments show that about 10% system-wide power can be saved, the voltage regulator area can be reduced by 30%, di/dt improves 49%, and the power pin count is reduced by 40% (≈ 20% reduction in packaging costs), with negligible performance degradation.
Mathematical Geosciences | 2016
M.J. Ramón; José Luis Briz; Emilio L. Pueyo; Oscar Fernández
Restoration of geological structures helps understand and validate the reconstruction of subsurface structures. In many restoration algorithms, the surface is triangulated and then unfolded, starting from an undeformed location (pin-element). The aim of this paper is to assess the impact of the pin-element location and triangulation of the mesh (density and type) on restoration by best fitting of finite elements, with and without a rotation constraint. The deformation of complex structures is simulated at laboratory scale. First, a reference mesh is set on the undeformed models. Then, a deformation is applied to obtain the new mesh coordinates using photogrammetry. Finally, the mesh is restored and the deformation calculated on the restored model. Comparing the actual and computed deformation, it is found that dense meshes can help locate expected deformation areas, if a rotation constraint is used to reduce error propagation. Mesh type and density seem to play a secondary role in the final result for smooth surfaces, but become relevant for highly deformed surfaces. Pin-element location influences the restoration result, especially when no rotation constraint is considered. Overall, the results suggest that the accuracy and reliability of restoration methods based on triangular meshes can be significantly improved by using a rotation constraint.
european conference on parallel processing | 2008
Luis Ramos; José Luis Briz; Pablo Ibáñez; Víctor Viñals
We explore different prefetch distance-degree combinations and very simple, low-cost adaptive policies on a superscalar core with a high bandwidth, high capacity on-chip memory hierarchy. We show that sequential prefetching aggressiveness can be properly tuned at a very low cost to outperform state-of-the-art hardware data prefetchers and complex filtering mechanisms, avoiding performance losses in hostile applications and keeping the pressure of the prefetching on the cache low, turning it out into a real implementation option for current processors.
Geological Society, London, Special Publications | 2016
M.J. Ramón; Emilio L. Pueyo; Guillaume Caumon; José Luis Briz
Abstract Providing that a primary and reliable record of the magnetic field and its reference in a deformed area exists, the incorporation of palaeomagnetic constraints in restoration methods reduces uncertainty of rotation because such constraints can be applied both before and after deformation. In this paper, we utilize palaeomagnetic data to improve an unfolding algorithm based on the parameterization of the surface using isometric constraints. This method is more robust than others based on piecewise restoration of a triangulated surface, which are dependent on the meshing and, especially, on the pin-element. A disadvantage of this approach is that parametric restoration is sensitive to the initial solution, which hampers results for complex non-coaxial or non-cylindrical structures. We show that the use of palaeomagnetism as the initial gradient of one of the parameters improves the results of the method. We use analogue models to test the method because the expected restoration result can be stated, since the initial surface is known. We study the restoration sensitivity to surface meshing and the initial palaeomagnetic orientation. All in all, the use of palaeomagnetic vectors in the studied analogue models achieves the best restoration results. The implementation of palaeomagnetic vectors is crucial to obtain reliable 3D restorations of complex structures.
systems, man and cybernetics | 1994
José Luis Briz; José Manuel Colom; M. Silva
Practical tools for the design, analysis and simulation of Petri net models improve significantly the applicability of this mathematical formalism to complex systems. Much thought has been given to the problem of building such tools in an efficient and reliable way. Linear enabling functions (LEFs) provide a basis to efficiently implement place transition weighted systems. Transitions are classified in several classes, and their enabling is characterized through linear functions that depends on the class. For some classes, a transformation must be applied, preserving the behaviour of the net system.<<ETX>>
international symposium on microarchitecture | 2006
Jesús Alastruey; José Luis Briz; Pablo Ibáñez; Víctor Viñals
Do the demands of new software outpace developments in hardware? Experiments with the behavior of SPEC CPU on-chip caches and data collection from a wide range of processors over time address this question and illuminate trends in software and hardware evolution