Ehsan K. Ardestani

ESESC: A fast multicore simulator using Time-Based Sampling

Architects rely on simulation in their exploration of the design space. However, slow simulation speed caps their productivity and limits the depth of their exploration. Sampling has been a commonly used remedy. While sampling is shown to be an effective technique for single core processors, its application has been limited to simulation of multi-program, throughput applications only. This work presents Time-Based Sampling (TBS), a framework that is the first to enable sampling in simulation of multicore processors with virtually no limitation in terms of application type (multi-programmed or multithreaded), number of cores, homogeneity or heterogeneity of the simulated configuration (4.99% error averaged across all the evaluated configurations). TBS also is the first to enable integrated power and temperature evaluation in statistically sampled simulation of multicore systems (with 5.5% and 2.4% error on average, respectively). We implement an architectural simulator based on TBS, called ESESC, that provides a holistic set of tools for a fair evaluation of different architectures.

Characterizing processor thermal behavior

Temperature is a dominant factor in the performance, reliability, and leakage power consumption of modern processors. As a result, increasing numbers of researchers evaluate thermal characteristics in their proposals. In this paper, we measure a real processor focusing on its thermal characterization executing diverse workloads. Our results show that in real designs, thermal transients operate at larger scales than their performance and power counterparts. Conventional thermal simulation methodologies based on profile-based simulation or statistical sampling, such as Simpoint, tend to explore very limited execution spans. Short simulation times can lead to reduced matchings between performance and thermal phases. To illustrate these issues we characterize and classify from a thermal standpoint SPEC00 and SPEC06 applications, which are traditionally used in the evaluation of architectural proposals. This paper concludes with a list of recommendations regarding thermal modeling considerations based on our experimental insights.

Fast thermal simulators for architecture level integrated circuit design

High temperatures and non-uniform temperature distributions have become a serious concern since they limit both performance and reliability of Integrated Circuits (IC). With computer architects concern to position microarchitecture blocks in a processor, faster thermal models can be developed at the cost of hiding finer grain details such as circuit or transistor level information. Several methods to quickly estimate the surface temperature profiles of microarchitecture blocks have been investigated in recent years. HotSpot simulator is widely used in computer architecture community. SESCTherm is another architecture level thermal simulator which has shown good performance and modularity in modeling. Recently Power Blurring (PB) method has been developed for both steady-state and transient thermal analysis of standard and 3D chips. While some of these methods are validated against finite element and Greens function based techniques, there are no detailed comparisons of the accuracy and speed for some common applications. In this paper we present the steady-state and transient temperature distributions calculated by these three architecture level thermal simulators. A detailed comparison taking into account the accuracy and the computation speed is performed. Our results indicate that Power Blurring has the potential to be a promising architecture level thermal simulator for fast calculation of temperature profile from the input power map in a realistic package which, in turn, is a key ingredient for full self-consistent simulations.

Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices

High-temperature and temperature nonuniformity in high-performance integrated circuits (ICs) can significantly degrade chip performance and reliability. Thus, accurate temperature information is a critical factor in chip design and verification. Conventional volume grid-based techniques, such as finite-difference and finite-element methods (FEMs), are computationally expensive. In an effort to reduce the computation time, we have developed a new method, called power blurring (PB), for calculating temperature distributions using a matrix convolution technique in analogy with image blurring. The PB method considers the finite size and boundaries of the chip as well as 3-D heat spreading in the heat sink. PB is applicable to both static and transient thermal simulations. Comparative studies with a commercial FEM tool show that the PB method is accurate within 2%, with orders of magnitude speedup compared with FEM methods. PB can be applied to very fine power maps with a grid size as small as 10 μm for a fully packaged IC or submicrometer heat sources in power electronic transistor arrays. In comparison with architecture-level thermal simulators, such as HotSpot, PB provides much more accurate temperature profiles with reduced computation time.

Sampling in Thermal Simulation of Processors: Measurement, Characterization, and Evaluation

Power densities in modern processors induce thermal issues that limit performance. Power and thermal models add complexity to architectural simulators, limiting the depth of analysis. Prohibitive execution time overheads may be circumvented using sampling techniques. While these approaches work well when characterizing processor performance, they introduce new challenges when applied to the thermal domain. This paper aims to improve the accuracy and performance of sampled thermal simulation at the architectural level. To the best of our knowledge, this paper is the first to evaluate the impact of statistical sampling on thermal metrics through direct temperature measurements performed at runtime. Experiments confirm that sampling can accurately estimate certain thermal metrics. However, extra consideration needs to be taken into account to preserve the accuracy of temperature estimation in a sampled simulation. Mainly because, on average, thermal phases are much longer than performance phases. Based on these insights, we introduce a framework that extends statistical sampling techniques, used at the performance and power stages, to the thermal domain. The resulting technique yields an integrated performance, power, and temperature simulator that maintains accuracy, while reducing simulation time by orders of magnitude. In particular, this paper shows how dynamic frequency and voltage adaptations can be evaluated in a statistically sampled simulation. We conclude by showing how the increased simulation speed benefits architects in the exploration of the design space.

Thermal-aware sampling in architectural simulation

Thermal behavior of modern processors is a first-order design constraint. However, accurate estimation of thermal behavior is time consuming, and techniques for accelerating performance simulations often yield inaccurate results when directly applied to thermal simulation, or do not reduce the thermal computation at all. This paper is the first to propose thermal sampling techniques. It can be integrated with existing phase-based and statistical-based architectural simulator sampling. The resulting simulator can perform accurate performance, power, and thermal characterization at close to 30 MIPS, on average, instead of 5 MIPS for the fastest sampling technique without thermal-aware sampling.

Cooling solutions for processor Infrared Thermography

Temperature is a key parameter due to its impact on timing, energy, and reliability. A setup to measure temperature in runtime with high spatial and temporal resolution would help to study the thermal behavior of processors. Currently, Infrared Thermography infrastructures has been developed to measure the temperature in real-time. Since the infrared opaque metal heat sinks need to be replaced with an infrared transparent heat sink in these setups, oil based cooling solutions have been proposed. However, oil is not a representative of a metal heat sink because measurement with oil based cooling can change the thermal behavior of the processor. In this paper, we discuss a representative oil based cooling solution, and show that it has the same thermal response as a metal heat sink.

An energy efficient GPGPU memory hierarchy with tiny incoherent caches

With progressive generations and the ever-increasing promise of computing power, GPGPUs have been quickly growing in size, and at the same time, energy consumption has become a major bottleneck for them. The first level data cache and the scratchpad memory are critical to the performance of a GPGPU, but they are extremely energy inefficient due to the large number of cores they need to serve. This problem could be mitigated by introducing a cache higher up in hierarchy that services fewer cores, but this introduces cache coherency issues that may become very significant, especially for a GPGPU with hundreds of thousands of in-flight threads. In this paper, we propose adding incoherent tinyCaches between each lane in an SM, and the first level data cache that is currently shared by all the lanes in an SM. In a normal multiprocessor, this would require hardware cache coherence between all the SM lanes capable of handling hundreds of thousands of threads. Our incoherent tinyCache architecture exploits certain unique features of the CUDA/OpenCL programming model to avoid complex coherence schemes. This tinyCache is able to filter out 62% of memory requests that would otherwise need to be serviced by the DL1G, and almost 81% of scratchpad memory requests, allowing us to achieve a 37% energy reduction in the on-chip memory hierarchy. We evaluate the tinyCache for different memory patterns and show that it is beneficial in most cases.

Managing Mismatches in Voltage Stacking with CoreUnfolding

Five percent to 25% of power could be wasted before it is delivered to the computational resources on a die, due to inefficiencies of voltage regulators and resistive loss. The power delivery could benefit if, at the same power, the delivered voltage increases and the current decreases. This article presents CoreUnfolding, a technique that leverages voltage Stacking to improve power delivery efficiency. Our experiments show that about 10% system-wide power can be saved, the voltage regulator area can be reduced by 30%, di/dt improves 49%, and the power pin count is reduced by 40% (≈ 20% reduction in packaging costs), with negligible performance degradation.

Enabling power density and thermal-aware floorplanning

With temperature being one of the main limiting factors in design of high performance processors, early evaluation of thermal effects in design stages is becoming a necessity. Floorplanning is an imperative step in the design process where thermal effects can be taken into account. This work studies a thermal-aware floorplanning scheme, with the goal of increasing both reliability and performance measures of the design. We show that a majority of thermal emergencies can be averted by a) leveraging the lateral heat transfer effects (as has been shown previously), and b) by reducing the power density of thermally critical blocks. The former becomes possible through moving, and modifying the aspect-ratio of the blocks in the floorplanning process. The latter, one of the key contributions of this work, is carried out through resizing of functional blocks in a controlled way. We also propose a selective power map generation method for the floorplanning process. In this method the time windows in which thermal emergencies occur guide the power map generation. As a result, we observed an 8.8% performance improvement, and a 40% reliability increase with the area overhead of just 3%.