José Luis Pino

Software synthesis for DSP using Ptolemy

Ptolemy is an environment for simulation, prototyping, and software synthesis for heterogeneous systems. It uses modern object-oriented software technology (in C++) to model each subsystem in a natural and efficient manner, and to integrate these subsystems into a whole. The objectives of Ptolemy encompass practically all aspects of designing signal processing and communications systems, ranging from algorithms and communication strategies, through simulation, hardware and software design, parallel computing, and generation of real-time prototypes. In this paper we will introduce the software synthesis aspects of the Ptolemy system. The environment presented here is both modular and extensible. Ptolemy allows the user to choose among various single- or multiple-processor schedulers.

A comparison of synchronous and cycle-static dataflow

We compare synchronous dataflow (SDF) and cyclo-static dataflow (CSDF), which are each special cases of a model of computation we call dataflow process networks. In SDF actors have static firing rules: they consume and produce a fixed number of data tokens in each firing. This model is well suited to multirate signal processing applications and lends itself to efficient static scheduling, avoiding the run-time scheduling overhead incurred by general implementations of process networks. In CSDF which is a generalization of SDF actors have cyclically changing firing rules. In some situations, the added generality of CSDF can unnecessarily complicate the scheduling. We show how higher-order functions can be used to transform a CSDF graph into a SDF graph, simplifying the scheduling problem. In other situations, CSDF has a genuine advantage over SDF: simpler precedence constraints. We show how this makes it possible to eliminate unnecessary computations and expose additional parallelism. We use digital sample rate conversion as an example to illustrate these advantages of CSDF.

A hierarchical multiprocessor scheduling system for DSP applications

This paper discusses a hierarchical scheduling framework which reduces the complexity of scheduling synchronous data flow (SDF) graphs onto multiple processors. The core of this framework is a clustering algorithm that decreases the number of nodes before expanding the SDF graph into a precedence directed acyclic graph (DAG). The internals of the clusters are then scheduled with uniprocessor SDF schedulers which can optimize for memory usage. The clustering is done in such a manner as to leave ample parallelism exposed for the multiprocessor scheduler. We have developed the SDF composition theorem for testing if a clustering step is valid. The advantages of this framework are demonstrated with several practical, real-time examples.

Hierarchical static scheduling of dataflow graphs onto multiple processors

Discusses a hierarchical scheduling framework to reduce the complexity of scheduling synchronous dataflow (SDF) graphs onto multiple processors. The core of this framework is a clustering technique that reduces the number of actors before expanding the SDF graph into an directed acyclic graph (DAG). The internals of the clusters are then scheduled with uniprocessor SDF schedulers which can optimize for memory usage. The clustering is done in such a manner as to leave ample parallelism exposed for the multiprocessor scheduler. The authors illustrate this framework with a real-time example that has been constructed in Ptolemy.

Automatic code generation for heterogeneous multiprocessors

This paper describes the use of Ptolemy to automatically generate code for heterogeneous multiprocessor systems. The framework presented lets the designer migrate from simulation to code generation while developing an application that is specified by constructing a dataflow graph. From primitive send and receive actors, the framework can automatically construct three classes of interprocessor communication (IPC) interfaces. The first type of interface uses a synchronous dataflow (SDF) parallel scheduler to partition and schedule the graph across the available processors. The second type of interface allows hierarchical use of cooperating schedulers within an application. Finally, the third interface uses the send and receive actors as an interface between code generation and simulation systems in Ptolemy. To illustrate the framework, we present an example of a heterogeneous architecture consisting of a workstation with multiple Motorola 56001 processors. We present the relative strengths and weaknesses of each type of interface.<<ETX>>

Mapping multiple independent synchronous dataflow graphs onto heterogeneous multiprocessors

We detail a method to facilitate development of real-time applications on heterogeneous multiprocessors. We introduce a new model of computation that allows for nondeterminate communication between independent dataflow graphs. The graphs may communicate in a manner that does not introduce data dependencies between them. We examine the implications of this model, introduce the necessary communication actors, and discuss scheduling techniques for multiple independent graphs. We also illustrate this model with some examples of real-time systems that have been constructed in Ptolemy.<<ETX>>

Efficient simulation of critical synchronous dataflow graphs

Simulation and verification using electronic design automation (EDA) tools are key steps in the design process for communication and signal processing systems. The synchronous dataflow (SDF) model of computation is widely used in EDA tools for system modeling and simulation in the communication and signal processing domains. Behavioral representations of practical wireless communication systems typically result in critical SDF graphs - they consist of hundreds of components (or more) and involve complex inter-component connections with highly multirate relationships (i.e., with large variations in average rates of data transfer or component execution across different subsystems). Simulating such systems using conventional SDF scheduling techniques generally leads to unacceptable simulation time and memory requirements on modern workstations and high-end PCs. In this paper, we present a novel simulation-oriented SDF scheduler (SOS) that strategically integrates several techniques for graph decomposition and SDF scheduling to provide effective, joint minimization of time and memory requirements for simulating large-scale and heavily multirate SDF graphs. We have implemented the SOS scheduler in the advanced design system (ADS) from Agilent Technologies. Our results from this implementation demonstrate large improvements in simulating real-world wireless communication systems (e.g. 3GPP, Bluetooth, 802.16e, CDMA 2000, and XM radio)

Multithreaded simulation for synchronous dataflow graphs

Synchronous dataflow (SDF) has been successfully used in design tools for system-level simulation of wireless communication systems. Modern wireless communication standards involve large complexity and highly-multirate behavior, and typically result in long simulation time. The traditional approach for simulating SDF graphs is to compute and execute static single-processor schedules. Nowadays, multi-core processors are increasingly popular for their potential performance improvements through on-chip, thread-level parallelism. However, without novel scheduling and simulation techniques that explicitly explore multithreading capability, current design tools gain only minimal performance improvements. In this paper, we present a new multithreaded simulation scheduler, called MSS, to provide simulation runtime speed-up for executing SDF graphs on multi-core processors. We have implemented MSS in the advanced design system (ADS) from Agilent Technologies. On an Intel dual-core, hyper-threading (4 processing units) processor, our results from this implementation demonstrate up to 3.5 times speed-up in simulating modern wireless communication systems (e.g., WCDMA3G, CDMA 2000, WiMax, EDGE, and Digital TV).

A mixed-mode vector-based dataflow approach for modeling and simulating LTE physical layer

Long Term Evolution (LTE) is one of the emerging technologies toward 4th generation mobile wireless networks. For LTE physical layer development, electronic system level (ESL) tools are widely used to assist design and verification processes. Among various modeling technologies underlying ESL tools, synchronous dataflow (SDF) and its related models of computation have been successfully used to model and simulate many wireless standards. However, LTE physical layer involves dynamically varying data processing rates that make SDF insufficient due to its constant-rate constraint. In this paper, we present a novel approach, called Mixed-mode Vector-based Dataflow (MVDF), to efficiently model and simulate LTE physical layer by exploring the matched-rate nature of LTE and by combining static and dynamic dataflow technologies. We have implemented MVDF in an ESL tool, called SystemVue, along with a complete LTE physical layer library. With the implementation, we are able to create LTE reference designs for performance measurements. Our simulation results successfully match the standard requirements and justify the capability of MVDF.

Interface synthesis in heterogeneous system-level DSP design tools

We describe a framework that constructs interfaces between simulation tools and real-time prototyping hardware in a high-level DSP synthesis environment. A goal of this work is to abstract the concept of the interface so that customized links are not required between each simulation and hardware engine. To support a new engine, the DSP system designer must define two pairs of communication primitives between the new tool and host workstation. The interface construction mechanism provides incremental compilation of subsystems in a system specification into the high-level DSP synthesis environment. We illustrate this framework with practical examples that have been constructed in Ptolemy.