José Luis Vázquez-Avila

Call admission and code allocation strategies for WCDMA systems with multirate traffic

In this paper, call admission and code allocation schemes are proposed to provide service differentiation in the forward link of wideband code-division multiple-access (WCDMA) systems. In particular, this paper proposes multiple leaf code reservation (MLCR) schemes, where different numbers of orthogonal variable spreading factor (OVSF) leaf codes (i.e., codes of the lowest layer of the OVSF code tree) are reserved to differentiate users with different bandwidth requirements. Leaf codes are only reserved for as long as the call admission process lasts. Once the decision of whether a new request is admitted or not has been made, a Code Dereservation procedure is carried out to increase flexibility in the code assignment phase. The performance of these MLCR strategies with/without code reassignments is then evaluated. Analysis shows that MLCR schemes are also useful in improving fair access among different traffic classes. In addition, perfect fair access among requests with different data rates can be achieved when code reassignments are jointly employed with the proposed OVSF-code reservation schemes.

Software Defined Networks-on-Chip for Multi/Many-Core Systems: A Performance Evaluation

By means of a management framework and programmable routing tables, Software Defined Network (SDN) architectures offer networks adaptability to todays computer systems. In Networks-on-Chip (NoC) based systems, management methods have been implemented as specific solutions unable to be reused in further designs. A Software Defined NoC (SDNoC) architecture will permit on-the-fly re/configuration and reduce Non-Recurring Engineering costs. In this paper, performance evaluations of a SDNoC through flit-accurate SystemC models are presented. We measure the average values of the configuration time (CT), global delay and throughput for various routing algorithms and packet injection rates.

Shifting the Network-on-Chip Paradigm towards a Software Defined Network Architecture

In the Many-Core era, parallel processing performance is generally limited by the communications infrastructures adaptability to the applications data dependencies. By means of a management framework, Software Defined Network (SDN) architectures offer such adaptability for conventional computer networks. However, Networks-on-Chip (NoC) management subsystems have been implemented as specific solutions unable to be reused in further designs. In this paper we applied SDN principles to propose a Software Defined NoC (SDNoC) architecture. This architecture is focused in abstraction layers and interfaces that permit its deployment in a modular fashion. Our proposal will orchestrate the complex multi-objective optimization to adjust on-chip networking to the applications requirements and data dependencies. This architecture allows the addition of other optimization engines without changing the software or hardware contained in underlying planes, then, Non-Recurring Engineering costs can be diminished.

NoC-based hardware function libraries for running multiple DSP algorithms

Currently, application-specific systems on chip (SoC) require complex digital designs, causing the validation process to increment, affecting the ever-narrower time-to-market. An approach to deal with this issue consists of using already-validated IP cores interconnected by a network on chip (NoC). However, the NoC is mostly used as part of an application-specific design, which implies wasting time in configuring the NoC for a particular application. With the aim of hiding these management problems from high-level (software) designers, in this paper, the use of a NoC as a hardware function library provider is studied. This requires the introduction of a new entity into the NoC, here called the Feeder-Collector, that acts as an intermediary between the system and the NoC. The advantages of this approach are shown by means of a case study, where an ad hoc implementation in contrasted with the proposed NoC approach, for three digital signal processing algorithms. Results show that, on average, resource of 43.68% can be achieved by using the proposed approach, while at the same time, Non-Recursive-Engineering costs are reduced.

Link quality-aware call admission strategy for mobile cellular networks with link adaptation

In this paper, the performance of mobile cellular systems with link adaptation (LA) is analytically evaluated. Half- and full-rate vocoders are considered in the analysis. Mathematical expressions for the new call blocking, handoff failure, and forced termination probabilities are obtained. To our knowledge, no similar analysis considering LA exists in the literature. Also, the link quality-aware dual fractional channel reservation (LQA DFCR) scheme is proposed. In LQA DFCR, user differentiation is implemented in terms of link quality. Preference is given to users with good link quality because they require fewer resources than users with bad link quality. Numerical results show that the proposed LQA DFCR scheme effectively increases system capacity: LQA DFCR achieves more than a 11% capacity gain relative to systems with the non priority scheme (NPS) and with LA, and approximately 3% relative to the fair access prioritisation scheme (FAPS) strategy. Numerical results also show that LA yields an approximately 18% capacity increase relative to a cellular system without LA when no admission control is employed (admission control strategies further increase system capacity.) The synergy between LA and admission control strategies yields more than a 31% capacity gain

Link quality-aware cut-off prioritisation strategy for GSM/GPRS networks with link adaptation

In this paper, the system level performance (teletraffic analysis) of a GSM/GPRS network where speech and data services coexist is analytically evaluated. In our work, link adaptation for both speech and data services, is considered in the system capacity assessment. For speech service, half- and full-rate vocoders are considered in the analysis. For data services, only those coding schemes that are currently used in practical GPRS systems are used in our analysis: CS-1 and CS-2. Also, a link quality-aware triple threshold reservation (LQA TTR) scheme is proposed. In LQA TTR, preference is given to data users on the good quality zone (CS2) because, on average, they require less time to be served relative to data users on the bad quality zone (CS-1). Numerical results show that the proposed LQA TTR scheme effectively reduces call blocking probabilities relative to the conventional multiple channel reservation strategy.

Synergy between admission control and link adaptation in integrated voice/data cellular networks

The capacity maximization of integrated voice/data wireless cellular communication systems with link adaptation (LA) is addressed using the GSM/GPRS system as a case study. Only coding schemes CS-1 and CS-2 are used. Two different quality zones differentiated by signal quality are used and mapped to the two coding schemes. Data users in the good quality zone make use of CS-2 only; data users in the bad quality zone make use of CS-1 only. Also, we provide an overview of reported system performance analyses of integrated voice/data cellular systems. Finally, a resource allocation strategy, called triple link quality-aware fractional channel reservation (TLQAFCR), is proposed; it differentiates data users in the different quality coverage zones. Numerical results show that TLQAFCR effectively increases system capacity relative to strategies without user location differentiation. This is because, in TLQAFCR, preference is given to data users in the good quality (CS-2) zone which, on average, retain resources less time than data users in the bad quality (CS-1) zone. Numerical results also show that the use of the LA technique increases approximately 20% data system capacity and that the synergy between admission control and link adaptation yields more than 387% capacity gain.

NI + Router Microarchitecture for NoC-based Communication Systems

Modern communication systems are characterized by intensive computation signal processing algorithms. System-on-Chip implementations of these systems are generally based on Networks-on-Chip (NoC). The router and Network Interface (NI) are the main elements of the NoC, but the router is the architecture most discussed in the literature. Here, a NI + router microarchitecture is presented. Our router implementation outperforms the previous work in operational frequency by a 20%. The NI usually is assumed as a simple wrapper, although results in this work show that the NI can consume almost twice resources than the router. This indicates that further discussions must be carried out for the design of NoC-based communication systems.

A fast discrete event simulation model for queueing network systems

Based on Lindleys recursive equations for G/G/1 systems, this paper proposes a Fast Discrete Event Simulation (FDES) model for queueing networks. Equations for multiplexer and de-multiplexer elements are presented, which allows to simulate not only tandem but queueing networks with an arbitrary topology. Time savings obtained with FDES could speed up the analyses of large-scale queueing network systems. Experimental results show that FDES modeling can be two orders of magnitude faster than their counterparts based on the event-scheduling for practical cases.

Unconventional signal processing architecture for reconfigurable on-chip communication systems

Algorithms for digital communication systems can be represented via a set of specialized signal processing (SP) blocks. Hence, in the implementation of these algorithms, the interconnection among the processing blocks aggregates complexity to the design. Usually, these interconnections are made through specialized glue logic, Point-to-Point (P2P) interconnections, Bus or a Network on Chip (NoC). Furthermore, the communications industrys trend is to move forward to Software Defined Radio (SDR) or reconfigurable communications SoC, which imposes hard constrains in the selected interconnection approach. Particularly, the management tasks directly influence the systems performance. Therefore, it is important to study the decision of leaving this administration to a dedicated processor or to a general purpose processor. Here, a NoC-based architecture is proposed to overcome the management problem. A Feeder-Collector, that takes out the reconfiguration and managerial tasks from the main CPU is introduced. This architecture creates a HW-based library of SP functions which simplifies software applications, without sacrificing performance. Analytical and simulation results show that our proposal achieves a high performance and the lowest CPUs load compared with P2P, Bus and conventional NoC interconnections.