Remberto Sandoval-Arechiga

Software Defined Networks-on-Chip for Multi/Many-Core Systems: A Performance Evaluation

By means of a management framework and programmable routing tables, Software Defined Network (SDN) architectures offer networks adaptability to todays computer systems. In Networks-on-Chip (NoC) based systems, management methods have been implemented as specific solutions unable to be reused in further designs. A Software Defined NoC (SDNoC) architecture will permit on-the-fly re/configuration and reduce Non-Recurring Engineering costs. In this paper, performance evaluations of a SDNoC through flit-accurate SystemC models are presented. We measure the average values of the configuration time (CT), global delay and throughput for various routing algorithms and packet injection rates.

Shifting the Network-on-Chip Paradigm towards a Software Defined Network Architecture

In the Many-Core era, parallel processing performance is generally limited by the communications infrastructures adaptability to the applications data dependencies. By means of a management framework, Software Defined Network (SDN) architectures offer such adaptability for conventional computer networks. However, Networks-on-Chip (NoC) management subsystems have been implemented as specific solutions unable to be reused in further designs. In this paper we applied SDN principles to propose a Software Defined NoC (SDNoC) architecture. This architecture is focused in abstraction layers and interfaces that permit its deployment in a modular fashion. Our proposal will orchestrate the complex multi-objective optimization to adjust on-chip networking to the applications requirements and data dependencies. This architecture allows the addition of other optimization engines without changing the software or hardware contained in underlying planes, then, Non-Recurring Engineering costs can be diminished.

NoC-based hardware function libraries for running multiple DSP algorithms

Currently, application-specific systems on chip (SoC) require complex digital designs, causing the validation process to increment, affecting the ever-narrower time-to-market. An approach to deal with this issue consists of using already-validated IP cores interconnected by a network on chip (NoC). However, the NoC is mostly used as part of an application-specific design, which implies wasting time in configuring the NoC for a particular application. With the aim of hiding these management problems from high-level (software) designers, in this paper, the use of a NoC as a hardware function library provider is studied. This requires the introduction of a new entity into the NoC, here called the Feeder-Collector, that acts as an intermediary between the system and the NoC. The advantages of this approach are shown by means of a case study, where an ad hoc implementation in contrasted with the proposed NoC approach, for three digital signal processing algorithms. Results show that, on average, resource of 43.68% can be achieved by using the proposed approach, while at the same time, Non-Recursive-Engineering costs are reduced.

Teletraffic analysis of access and transmission rate fairness in EGPRS networks

In this paper, the performance of three fair resource allocation strategies for packet data transmission in EDGE/GPRS networks are mathematically analyzed. The strategies aim at achieving, respectively, fair access, fair transmission rate and, simultaneous fair access and transmission rate. The differences in terms of QoS and GoS caused by link adaptation (LA) and multi-slot allocation experienced by data users in EGPRS networks is smoothed by these strategies through the use of multiple resource reservation and/or dynamic resource allocation strategies, which, at the same time, compensate users with poor radio channel conditions. Also, the performance of the proposed strategies is evaluated by means of teletraffic analysis tools in terms of packet blocking probabilities and throughput

Dynamic resource allocation in integrated voice/data wireless networks with link adaptation

In this paper, the performance of dynamic resource allocation and channel de-allocation in integrated voice/data wireless networks with link adaptation is mathematically analyzed and evaluated. To our knowledge, all previous related works published in the literature have considered only link adaptation (LA) or dynamic resource allocation (DRA) separately. Additionally, a DRA strategy with link quality-aware prioritized channel de-allocation (called DRA LA DAS) is proposed. With the DRA LA DAS scheme that calls with the greatest number of channels and the worst link quality are degraded first. In this way, in DRA LA DAS preference is given to data users with good quality link which, on average, retain resources less time than data users with bad quality link. Numerical results show that the proposed DRA LA DAS strategy significantly improves system performance. The GSM/GPRS system is used as a case study. The GSM voice new call blocking and forced termination probabilities, GPRS packet dropping probability, average GPRS packet transmission time, and channel utilization are analyzed

NI + Router Microarchitecture for NoC-based Communication Systems

Modern communication systems are characterized by intensive computation signal processing algorithms. System-on-Chip implementations of these systems are generally based on Networks-on-Chip (NoC). The router and Network Interface (NI) are the main elements of the NoC, but the router is the architecture most discussed in the literature. Here, a NI + router microarchitecture is presented. Our router implementation outperforms the previous work in operational frequency by a 20%. The NI usually is assumed as a simple wrapper, although results in this work show that the NI can consume almost twice resources than the router. This indicates that further discussions must be carried out for the design of NoC-based communication systems.

A fast discrete event simulation model for queueing network systems

Based on Lindleys recursive equations for G/G/1 systems, this paper proposes a Fast Discrete Event Simulation (FDES) model for queueing networks. Equations for multiplexer and de-multiplexer elements are presented, which allows to simulate not only tandem but queueing networks with an arbitrary topology. Time savings obtained with FDES could speed up the analyses of large-scale queueing network systems. Experimental results show that FDES modeling can be two orders of magnitude faster than their counterparts based on the event-scheduling for practical cases.

Unconventional signal processing architecture for reconfigurable on-chip communication systems

Algorithms for digital communication systems can be represented via a set of specialized signal processing (SP) blocks. Hence, in the implementation of these algorithms, the interconnection among the processing blocks aggregates complexity to the design. Usually, these interconnections are made through specialized glue logic, Point-to-Point (P2P) interconnections, Bus or a Network on Chip (NoC). Furthermore, the communications industrys trend is to move forward to Software Defined Radio (SDR) or reconfigurable communications SoC, which imposes hard constrains in the selected interconnection approach. Particularly, the management tasks directly influence the systems performance. Therefore, it is important to study the decision of leaving this administration to a dedicated processor or to a general purpose processor. Here, a NoC-based architecture is proposed to overcome the management problem. A Feeder-Collector, that takes out the reconfiguration and managerial tasks from the main CPU is introduced. This architecture creates a HW-based library of SP functions which simplifies software applications, without sacrificing performance. Analytical and simulation results show that our proposal achieves a high performance and the lowest CPUs load compared with P2P, Bus and conventional NoC interconnections.

Teletraffic Analysis of Access and Transmission Rate Fairness Policies for Integrated Voice/Packet Data Transmission in Wireless Networks with Link Adaptation

In this paper, the performance of three different fair resource allocation strategies for packet data transmission in wireless networks with link adaptation (LA) is mathematically analyzed. The strategies aim at achieving fair access, fair transmission rate or simultaneous fair access and transmission rate. As a case study, the performance of the considered strategies is evaluated in GSM/EGPRS networks in terms of call blocking probability for voice packet data users and system throughput. However, the analysis is valid for any Radio Transmission Technology that uses LA techniques. For the mathematical analysis, packet data traffic (i.e., IP) is modeled as a process showing pseudo-long range dependence. In particular, to capture their bursty nature, packet data arrivals are considered to follow a Modulated Markov Poisson Process (MMPP) process. Numerical results show that voice calls get lower blocking probability than data packet transmissions when a fair access resource allocation strategy is used. Also, a trade off between (access and/or transmission rate) fairness and system utilization is observed. Finally, it is also shown that high grade of burstiness significantly degrades the system performance.