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Dive into the research topics where José Soares Augusto is active.

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Featured researches published by José Soares Augusto.


european design and test conference | 1995

Fully automatic DC fault dictionary construction and test nodes selection for analogue fault diagnosis

José Soares Augusto; Carlos Beltrán Almeida

Although the Fault Dictionary (FD) is one of the oldest approaches in analogue fault diagnosis, it is the most used in industrial environments. We present a fully automatic system that selects a minimum set of test nodes and gives the range of their voltages for each fault. All the information it uses is in three input files given by the test engineer: the circuit description (similar to the SPICE), the fault list and the tolerance file.<<ETX>>


Vlsi Design | 2008

A tool for single-fault diagnosis in linear analog circuits with tolerance using the T-vector approach

José Soares Augusto; Carlos Beltrán Almeida

In previous works of these authors, a technique for doing single-fault diagnosis in linear analog circuits was developed. Under certain conditions, one of them assuming nominal values for the circuit parameters, it was shown that only two measurements taken on two selected circuit nodes, at a single frequency, were needed to detect and diagnose any parametric fault. In this paper, the practical value of the technique is improved by extending the application to the diagnosis of faults in circuits with parameters subject to tolerance. With this in mind, single parametric faults with several strengths are randomly injected in the circuit under study and, afterwards, these faults are diagnosed (or the diagnosis fails). Results are reported on a simple active filter. Conclusions are drawn about the robustness and effectiveness of the technique.


international symposium on circuits and systems | 1994

New algorithms in piecewise linear resistive simulation

José Soares Augusto; Carlos Beltrán Almeida

This paper presents a piecewise linear (PWL) resistive simulator. It uses an efficient algorithm to obtain the constraint matrix of a linear multiport from the modified nodal analysis (MNA) equations and a novel algorithm to solve the generalized linear complementarity problem (GLCP) that arises from the PWL circuit equations.<<ETX>>


Archive | 2015

Arduino Implementation of Automatic Tuning in PID Control of Rotation in DC Motors

Rodrigo Nuno Mendes Antunes; David Santinhos Ferreira; Inês Isabel Gonçalves Santos; Ana Rita Das Neves Sousa; José Soares Augusto

In this paper is described a laboratory control experiment that targets, through a practical ”hands-on” approach, several important control matters: PID control; digital control; controller design; automatic tuning; nonlinear control and the describing function; and, above all, the practical implementation issues which arise in real projects. Both hardware and software scopes of the project are presented and discussed. The inexpensive Arduino is used as the implementation platform, what helps the interested readers in developing a similar experiment.


european conference on circuit theory and design | 2011

Efficient time domain analogue fault simulation targeting nonlinear circuits

José Soares Augusto

It is presented an efficient single fault simulation methodology for dynamic analogue circuits with nonlinear resistive elements. It is suitable for the simulation-before-test of thousands of faulty circuits, such as when building fault dictionaries. The proposed strategy merges techniques with efficiency already been demonstrated with prototype simulators: one supports nonlinear resistive circuits; and the other supports linear dynamic circuits. The results obtained with these partial implementations, as well as the expected efficiency of the global implementation are discussed. The partial implementations have shown speed-up in fault simulation better than one order of magnitude (in linear dynamic circuits) and better than two orders of magnitude (in nonlinear resistive circuits).


international conference on electronics circuits and systems | 1998

Circuit equations for fast fault simulation and diagnosis of linear circuits

José Soares Augusto; Carlos Beltrán Almeida

In this paper, we propose a Modified Nodal Analysis (MNA) based method for writing the circuit equations in the presence of a single fault which is suited for the efficient fault simulation and diagnosis using a Fault Dictionary (FD). The fault simulation equations are obtained from a cheap modification of the LU factors of the nominal matrix. The theoretical speed-up in the simulation of one fault, compared to the simulation time of the nominal circuit, is in the order of /spl sim/n for full n/spl times/n matrices. The reported experimental results validate the method.


Archive | 2000

TESTABILITY ISSUES IN THE CMS ECAL UPPER-LEVEL READOUT AND TRIGGER SYSTEM

Carlos Beltrán Almeida; Isabel C. Teixeira; J. Varela; José Soares Augusto; Marcelino B. Santos; Nuno Cardoso


i-ETC : ISEL Academic Journal of Electronics Telecommunications and Computers | 2017

The Interface and Control System of the Upgraded HVOpto/HVRemote Card of the TileCal

José Soares Augusto; C. Rato; L. Gurriana; L. Seabra; A. Gomes; Guiomar Evans; A. Maio


Archive | 2017

CONTROL SYSTEM FOR ATLAS TileCal HVRemote BOARDS

Filipe Manuel Pedro Martins; Luis Filipe Oleiro Seabra; José Soares Augusto; A. Gomes; Catia Sofia Pinto Silva Rato; Joao Maria Almendra Sabino; A. Maio; Guiomar Evans; Luis Gurriana


Procedia Technology | 2014

Emulation in FPGA of G-Link Chip-set of Tile Calorimeter Electronic System☆

José Delgado Alves; J.A. Silva; Guiomar Evans; José Soares Augusto

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A. Gomes

University of Lisbon

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A. Maio

University of Lisbon

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J. Varela

University of the Algarve

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