Guiomar Evans

A Two-Stage Fully Differential Inverter-Based Self-Biased CMOS Amplifier With High Efficiency

A two-stage fully differential CMOS amplifier comprising inverters as input structures and employing self-biasing techniques is presented. The proposed amplifier benefits from an optimum compensation through time-domain optimization which permits achieving high energy efficiency. Moreover, it achieves the highest efficiency of its class and although it relies on a quasi-class-A topology, it is comparable to class-AB amplifiers. Detailed circuit analyses such as differential-mode, common-mode feedback, noise, slew rate, and input/output range are carried out. Based on these analyses, a manual design methodology and a genetic algorithm based optimization are presented. Finally, the most relevant experimental results for an integrated circuit prototype designed in a 0.13 μm 1.2 V standard CMOS technology are shown.

Two-stage fully-differential inverter-based self-biased CMOS amplifier with high efficiency

This paper describes a novel two-stage fully-differential CMOS amplifier comprising two self-biased inverter stages, with optimum compensation and high efficiency. Although it relies on a class A topology, it is shown through simulations, that it achieves the highest efficiency of its class and comparable to the best class AB amplifiers. Due to the self-biasing, a low variability in the DC gain over process, temperature, and supply is achieved. A detailed circuit analysis, a design methodology for optimization and the most relevant simulation results are presented, together with a final comparison among state-of-the-art amplifiers.

ADC built-in-self-test based on a pseudorandom uniform noise generator

This paper describes a digital built-in-self-test (BIST) solution to ADC dynamic performance testing. The proposed ADC BIST system is based in a uniform histogram approach to test the linearity of ADCs. A pipeline ADC with a resolution of 10 bits, a DAC with the same resolution as the ADC under test and the proposed BIST scheme were modeled and simulated in MATLAB to prove its validity. Several 32 bits pseudorandom uniform noise generators were evaluated. When compared with the Gaussian histogram approach, the obtained results show that the error on the maximum INL is 0.13 LSB for the Mersenne twister pseudorandom uniform noise generator and an adequate statistical significance is obtained with a quarter of the samples. Additionally, the number and complexity of the circuits are reduced.

New simple digital self-calibration technique for pipeline ADCs using the internal thermal noise

This paper describes a new digital-domain self- calibration technique for high-speed pipeline A/D converters using the internal thermal noise as input stimulus. This low- amplitude noise is amplified and recycled by the ADC itself and, due to the successive foldings, it is naturally converted into uniform noise. This noise is then used to calculate the required calibrating-codes. As an example, the calibration of a 13-bit pipeline ADC shows that the overall linearity can be significantly improved using this technique.

Low-voltage low-power CMOS analogue circuits for Gaussian and uniform noise generation

A CMOS analogue circuit for Gaussian noise generation as well as a novel circuit for transforming Gaussian noise into uniform noise, both designed for operating with a supply voltage of 1.5V, are presented. Both circuits are optimized for a 0.35 /spl mu/m standard CMOS technology using an equation-based design methodology based on genetic algorithms. Electrical simulations demonstrate that high noise amplitudes together with reasonable bandwidths can be achieved with relatively low power dissipation. Potential applications include self-calibration and on-chip self-testing of video-rate analogue-to-digital converters.

On-chip built-in self-test of video-rate ADCs using Gaussian noise

This paper presents a new method to perform built-in-self-test (BIST) to measure the DNL, INL and the output noise of an ADC. The technique uses a Gaussian noise source as input stimulus and a simple algorithm based in precalculated tables (on-chip ROMs) for the DNL and INL tests. The results of the proposed BIST algorithm are compared with other standard tests. The simplicity of the digital circuitry together with other advantages pointed-out, clearly demonstrate the attractiveness of the proposed technique.

On-Chip Built-In Self-Test of Video-Rate ADCs Using a 1.5 V CMOS Gaussian Noise Generator

A new method to perform built-in self-testing of the linearity and noise of ADCs is proposed. The technique uses an integrated CMOS Gaussian noise source as input stimulus together with a simple algorithm based in pre-calculated ROM tables for the DNL/INL measurements. The measured results of the integrated low-voltage noise generator are described. The evaluation of the proposed algorithm is demonstrated through a commercial 10-bit, 4OMS/s ADC and compared with the conventional histogram method using sine waves as input signal. The simplicity of the noise generator and of the digital circuitry together with other advantages pointed-out, clearly demonstrate the attractiveness of the proposed technique.

A digital pseudorandom uniform noise generator for ADC built-in self-test

This paper presents a digital pseudorandom uniform noise generator (UNG) for a built-in self-test (BIST) solution to ADC static performance test. A 32 bits Mersenne-Twister pseudorandom uniform noise generator [1] was implemented in a FPGA and evaluated to prove its validity in a proposed ADC BIST solution [2]. A pipeline ADC and a DAC, both with a resolution of 10 bits and the BIST solution were modeled and simulated in MATLAB. The obtained results were compared with the ADC static test and the error on the maximum INL is 0.19 LSB, when the implemented UNG is used. Furthermore, the results show that an adequate statistical significance is obtained for the 10 bits ADC and this test can be done with just 1/4 of the samples if a digital UNG is used instead of a Gaussian noise generator [3]. Additionally, the number and complexity of the noise generator and the BIST circuits are quite reduced, so this input stimulus is a good on-chip solution.

Efficient digital self-calibration of video-rate pipeline ADCs using white Gaussian noise

A digital-domain self-calibration technique for video-rate pipeline A/D converters based on a white Gaussian noise input signal is presented. The implementation of the proposed algorithm requires simple digital circuitry. An application design example of the self-calibration of a 12b, 40 MS/s CMOS pipeline ADC is shown to illustrate that the overall linearity of the ADC can be highly improved using this technique.

Digital pseudorandom uniform noise generators for ADC histogram test

This paper presents the evaluation of two different digital pseudorandom uniform noise generators (UNGs) applied to ADC histogram test. Two 32 bits pseudorandom uniform noise generators, a Mersenne-Twister (MTW) and a Linear Feedback Shift Register (LFSR), were implemented on a FPGA and evaluated to prove its validity in a proposed ADC built-in self-test (BIST) [1,2]. The BIST solution is based in the histogram method and the obtained results were compared with the ADC standard static test and with a histogram test using Gaussian noise as stimulus. A pipeline ADC and a DAC, both with a resolution of 10 bits, the Gaussian noise generator and the BIST solution were modeled and simulated in MATLAB. The obtained results shown that the histogram test with an UNG as a stimulus could be a powerful method to characterize 10 bits ADCs with the accuracy needed. Compared with the Gaussian histogram test, the number and complexity of the circuits is quite reduced and an adequate statistical significance is obtained with a quarter of samples, therefore the time required for tests is reduced.