Josef Fazekas

Quantifying charging damage in gate oxides of antenna structures for WLR monitoring

Abstract A new method to quantify the reliability risk for gate oxide with plasma induced charging damage (PID) is established. Based on existing antenna test methodology the quantity of inflicted damage is expressed in a physical meaningful number by means of a simple model applicable for thick oxides (>5 nm). This model takes trap activation, trap filling, detrapping and also traps generation under constant current test condition (“revealing stress”, “diagnostic stress”) into account. For the corresponding development of the measurable external supply voltage with time an equation is derived. Experimental test data from different oxide thicknesses are fitted to this model equation to obtain its main parameters, the cross section values. These cross section values describe the probabilities for the different trap/detrap processes during stress. Cross section values thus found extend published data for lower electric fields to high electric fields necessary for a fast test. The number of plasma induced traps, which was added to the oxide during wafer processing, can now be determined by applying an electron trapping rate (ETR) test method, and combining it with our dynamic trap generation/filling model. The obtained number of PID related traps opens a path to calculate the corresponding reduction of oxide lifetime. Real measurement data are used to illustrate the method and its applicability to fast wafer level reliability (fWLR) monitoring.

WLR monitoring methodology for assessing charging damage on oxides thicker than 4nm using antenna structures

In this paper a structured scheme of antenna test measurements and data analysis for production monitoring applications will be presented. It is taking into account that usually in a production environment no test chip but a limited number of scribe line modules are available. Scribe line modules allow for placement into most of the products without wasting productive silicon area. The focus is on systematic data evaluation and the possibility to use this method for a discussion and generation of a JEDEC standard on Plasma Induced Damage (PID).

Multi-purpose EM test structure with electrical verification of the failure spot demonstrated using SWEAT for fast wafer level reliability monitoring

A multi-purpose electromigration test structure designed for advanced fast wafer level reliability tests is described in this work. It is shown that different failure location and failure modes can be detected electrically by this test structure which is beneficial for early technology development as well as productive in-line monitoring. A carefully designed test structure guarantees the ability to test for different electromigration failure modes (upstream, downstream). The presented experimental data focuses on the investigation of different process splits.