Andreas Martin

An introduction to fast wafer level reliability monitoring for integrated circuit mass production

The continuous verification of process reliability is essential to semiconductor manufacturing. The tool that accomplishes this task in the required short time is the fast wafer level reliability monitoring (fWLR). The basic approaches for this task are described in this introductory overview. It summarizes sampling plans, discusses the feasibility of using fWLR for screening and describes the data assessment and application of control cards. Beyond these general topics many of the fWLR stress methods are described in detail: Dielectric stressing by means of an exponential current ramp is compared to ramped voltage stress. Especially for thin oxides the methods differ regarding the soft breakdown detection and the time they consume. Another task of fWLR is the detection of plasma induced damage, which can be achieved by applying a revealing stress to MOSFETs with antenna. The design challenges of the structures and the test method as well as the data assessment are described in detail. An important section deals with fWLR for interconnects. In this section the appropriate test structures (including thermal simulations) are illustrated and fast electromigration stresses are discussed and the details of standard wafer level electromigration accelerated test (SWEAT) are included. For contacts and vias a simple method to check reliability is presented. Finally the monitoring of device reliability is treated. It is shown that using indirect parameters that correlate well to standard parameters such as the drain current can be beneficial for fWLR. For both, the interconnects and the devices, it is essential to have locally heated test structures in order to keep the stress time low. The detection and verification of mobile ions can also be performed with such a self-heated structure. For the described methods examples are given to illustrate the usefulness.

Ramped current stress for fast and reliable wafer level reliability monitoring of thin gate oxide reliability

Abstract A ramped dielectric stress measurement, suitable for fast wafer level reliability (fWLR) monitoring, is assessed for thin gate oxide thicknesses down to 2.2 nm. Severe difficulties usually occur for the reliable detection of soft/hard breakdown in a short time interval and due to high direct tunneling currents. These are discussed and an exponentially ramped current stress is introduced tackling the problems. Early oxide fails were covered by a fast voltage ramp carried out before the current ramp. The advantages of the method are highlighted which has already been implemented for fWLR monitoring in high volume production on scribe line structures.

Fast productive WLR characterisation methods of plasma induced damage of thin and thick MOS gate oxides

The main goal of this work is to present a sensitive method for the testing of PID which is applicable to all oxide thicknesses and types of MOS transistors

MOS transistor characteristics and its dependence of plasma charging degradation on the test structure layout for a 0.13µm CMOS technology

The influence of interconnects and the pad stack on measured Metal-Oxide-Semiconductor (MOS) transistor parameter and their reliability degradation cannot always be neglected. The underlying effect is Plasma-Induced-Damage (PID) from the parasitic antennas connected to the MOS gate electrode. Usually, a protection diode is employed to avoid this. However, for some stress and measurement sequences a diode at the gate is not desirable. An alternative method - a layout optimisation is presented and discussed.

Polysilicon resistive heated scribe lane test structure for productive wafer level reliability monitoring of NBTI

A polysilicon resistive heated test structure was designed with a MOSFET embedded between two polysilicon heater stripes. A 4-terminal metal resistor above the heaters allows temperature control via the temperature coefficient of the resistance. A stress algorithm performs simultaneous thermal and electrical stress. The real device temperature is gained by a comparison of the temperature measured at the metal level and the pn-junction temperature measured by the forward diode characteristics. Bias Temperature Instability stress results from this structure are presented.

Fast and reliable WLR monitoring methodology for assessing thick dielectrics test structures integrated in the kerf of product wafers

In this work the optimisation of an in-line stress for thick dielectric layers, SMU set up, tester equipment and layout of test structures for fast WLR Monitoring is described. It is shown that a current ramp is the optimum solution to avoid any influence on adjacent chips from the stress, large melted areas of the test structures and/or the melting of the interconnect to the structure. The work focuses on Metal-Insulator-Metal capacitors, but similar observations can be also obtained from thick MOS gate oxides.

Degradation and recovery of variability due to BTI

Abstract BTI parameter degradation of MOSFETs shows a statistical variation. The distribution of the threshold voltage V th after NBTI stress originates from a convolution of the distribution of the virgin devices together with the additional distribution of the BTI degradation itself. The variability of the V th (and other electrical parameters) of the virgin devices bases on process induced fluctuations of dopant atoms, oxide thickness, channel length, etc. Mizuno et al. (1994) [1]. The dependence on the transistor size is proven by several publications [e.g. 2,3]. The variability of the BTI parameter degradation itself and the convolution are not fully understood yet and need further investigation. The impact of the recovery behavior on the distribution of the V th - values is, to our knowledge, not yet studied at all. In this paper we investigate the increase (degradation) of variability due to NBTI and the statistical behavior of V th after end of stress (recovery). Furthermore we analyze the dependency of the additional variability of V th on the transistor size and geometry. For the necessary statistical relevance we perform NBTI experiments with a special smart array test-structure at a large amount of pMOSFETs with various geometries. We prove our results for a second technology node with a different oxide thickness. We demonstrate for the first time that also the induced additional variability recovers. Furthermore we show that the variability of pMOSFETs after NBTI depends not only on the size of the active area ( w × l ) but also on its geometry ( w/l ).

On the impact of the layout of MOSFET test-structures on NBTI-, PBTI- and HCS-lifetime due to PID

We introduce and discuss in our paper an alternative to protection diodes and compare it with different sizes and placements of diodes. In contrast to other PID publications we do not focus on the PID itself but on the impact on full transistor-lifetime estimations. We evaluate long-term NBTI, PBTI and HCS experiments.

Assessing oxide reliability targets with fast WLR measurements

Abstract In this article, oxide reliability targets are discussed, and the significance of the extrinsic branch of a bimodal Weibull plot is critically described. The slope of the extrinsic branch plays an important role, and it is demonstrated that a worst case slope can be determined for extrapolation purpose. A strategy is laid out for the confirmation of the oxide reliability requirements.

Impact factors for BTI lifetime predictions

For accurate Bias Temperature (BTI) lifetime assessments a lot of aspects have to be considered correctly. Detailed requirement profiles, proper designed test-structures, accurate measurement techniques, correct consideration of recovery, and a deep understanding of circuit functions are the most important impact factors for a safe and accurate reliability assurance. This review-paper will address these issues for BTI lifetime predictions. It will discuss both, hazards like adulterant influences of measurement delay or parasitic Plasma Induced Damage (PID) of test-structures as well as opportunities like the s-curve behavior of AC-stress. Finally, some simple guidelines are set up.