Josef S. Watts

Modeling of Variation in Submicrometer CMOS ULSI Technologies

The scaling of semiconductor technologies from 90- to 45-nm nodes highlights the need for accurate and predictive compact models that address the regime where small-scale physical effects become dominant. These demanding requirements on compact models extend beyond the core model to a suite of design tools that include extraction tools and statistical methods to account for unpredictable variation (e.g., random dopant fluctuations and polysilicon linewidth variation) and predictable variation (e.g., transistor response differences that are layout dependent). Layout-dependent or local environment differences are driven by factors such as lithography and novel performance-enhancing process techniques such as dual-stress nitride liner films. Sources of variation such as rapid thermal annealing temperature, low-frequency noise, and modeling of back-end-of-line elements need to be considered. The modeling of intradie and interdie variations, updated for small geometries, should be properly positioned in the design flow. This paper presents the challenges and results of compact modeling at the 65-nm node and beyond

Benchmark Tests for MOSFET Compact Models With Application to the PSP Model

This paper presents the results of several qualitative ldquobenchmarkrdquo tests that were used to verify the physical behavior of the PSP model and its usefulness for future generations of CMOS IC design. These include newly developed tests and new experimental data stemming from low-power, RF, mixed-signal, and analog applications of MOSFETs.

Netlisting and Modeling Well-Proximity Effects

In advanced CMOS technologies, transistor characteristics depend not only on the layout of the device itself but also on the layout of the adjacent structures. For the compact model to accurately predict circuit behavior, it needs information about the transistor and the structures surrounding it. For the simulator to efficiently handle a large number of transistors, the information about the surrounding layout must be reduced to a small number of parameters for each transistor instance. The parameters must be such that they can be efficiently calculated from the layout by the layout-versus-schematic tool. This paper describes the solution chosen by the Government Electronics and Information Technology Association Compact Model Council for modeling the effect of well edges near a transistor and proposes general guidelines for efficient solutions for modeling other proximity layout effects

PSP-SOI: A Surface Potential Based Compact Model of Partially Depleted SOI MOSFETs

This paper reports recent progress on partially depleted (PD) SOI modeling using a surface potential based approach. The new model, called PSP-SOI, is formulated within the framework of the latest industry standard bulk MOSFET model PSP. In addition to its physics-based formulation and scalability inherited from PSP, PSP-SOI captures SOI specific effects by including a floating body simulation capability, a parasitic bipolar model, and self-heating. A nonlinear body resistance is included for modeling body-contacted SOI devices. The PSP-SOI model has been extensively tested on several PD/SOI technologies.

Scalable thermal resistance model for single and multi-finger silicon-on-insulator MOSFETs

This paper presents a thermal resistance model for silicon-on-insulator MOSFETs. The proposed model accounts for various heat dissipation paths in the device accurately and is accurate for both multi and single finger devices. Model development is based on carefully designed test structures to account for different heat dissipations paths. Improvement in the drain current fits across devices when using proposed model over standard BSIMSOI4.3 validates the model.

Enhancing Productivity by Continuously Improving Standard Compact Models

The design of an integrated circuit requires the efforts of a large number of people with a wide range of skills. The compact model is a communication tool by which the designer of transistors, resistors and other circuit elements tells the designer of circuits how the circuit elements behave. Without this information the circuit design would be a trial and error process and modern electronics would be impossible. High quality, industry standard compact models enhance the productivity of the industry by enabling precise communication between any device design team, and any circuit design team, anywhere in the world. To be useful for leading edge design the compact model must keep up with the pace of semiconductor technology innovation. This is the great challenge for the Compact Model Council. It is only possible because the CMC creates collaboration between academics, semiconductor foundries, EDA vendors and circuit designers

Modeling circuit variability

In order to design integrated circuits which can be manufactured with high yield the variations which can occur during manufacturing must be included with the compact models. The manufacturing variations comprise a complex correlated set of statistical distributions. This paper presents some of the current options and challenges in modeling variation. Improving the prediction of statistical circuit behavior will require coordinated improvement in models, netlisting tools and simulators.

Distortion Simulations with the PSP Model: Common-Gate Circuits

We present extensive simulations of distortion in common-gate configured FETs, operated around Vds=0 V, using the new PSP MOSFET model Results are compared to measurements. We show that as a FET is configured into an increasingly more realistic circuit, that the PSP models distortion performance improves correspondingly and that it can predict intermodulation distortion within ~3dB of measured data. Third, we quantify, for the first time, to what extent the intermodulation distortion, as represented by IIP3, can be improved by increasing the gate length (L) while scaling the width (W) to maintain the same Rds for constant insertion loss. We show that the magnitude of the 3rd derivative and IIP3 level off quickly with increasing L.

Timing qualification of a 0.25-/spl mu/m CMOS ASIC library using BSIM3 FET models

Extensive circuit-level model-to-hardware correlation using BSIM3 FET models is shown for the first time. We demonstrate that the models are capable of achieving error percentages in single digits across a wide range of circuit types and environmental conditions on devices with 0.18-/spl mu/m nominal L/sub eff/ in a 0.25-/spl mu/m generation CMOS technology. Further, we verify the model can accurately simulate hardware which has intentionally varied L/sub eff/ and V/sub t/ for the purpose of simulating long term process variation. Additionally, a unique statistical analysis technique for determining model error contributors is presented. Finally, a rigorous new methodology for the timing qualification of an ASIC library is described.

A 130nm RFSOI technology with switch, LNA, and EDNMOS devices for integrated front-end module SoC applications

The cellular frequency spectrum has become increasingly complex with over 50 frequencies in LTE standards. To reduce costs in the front end module the switch has migrated from a III-V PHEMT base to a silicon solution in RFSOI. While many providers have focused on a 180nm base technology node for the RFSOI there has been an increasing move to more advanced nodes to solution the logic requirements of the cellular standards. In addition there has been a strong interest in migrating to an SOC solution in RFSOI. In this paper a 130nm RFSOI technology is presented with high performance and low noise body tied 1.5V NMOS for LNA devices with a novel method of body contacting, low Ron*Coff NMOS for antenna switch and state of the art EDNMOS with fT of 38GHz and BVdss of 14V BVdss for integrated PA application. Specific results presented include characterization of the switch, LNA, and Power Amplifier devices.