Kok Wai Chew

Characterization and comparison of PECVD silicon nitride and silicon oxynitride dielectric for MIM capacitors

In this letter, we report on the electrical characteristic and the comparison of the metal-insulator-metal (MIM) capacitors with PECVD silicon nitride (SiN) and silicon oxynitride (SiON). Both capacitors are found to exhibit low leakage and high breakdown field strength, as well as absence of dispersive behavior, good linearity, and comparable quality factor behaviors.

Characterization and comparison of two metal-insulator-metal capacitor schemes in 0.13 /spl mu/m copper dual damascene metallization process for mixed-mode and RF applications

In this paper, we report on two manufacturable, low-cost MIM capacitor structures with Cu and Ta bottom electrode for 0.13 /spl mu/m 6-level Cu-metallization technology. The quality factor (Q) of the MIM capacitor with SiN dielectric directly deposited on the Cu surface is found to be twice as high as that with Ta bottom plate. Both the Cu and Ta bottom-plate capacitors were found to exhibit low leakage and high breakdown field strength characteristics, as well as absence of dispersive behaviour, and good voltage and temperature linearity. The impact of the Cu surface roughness on the dielectric reliability was reduced by optimizing SiN precursor gas flow.

Effects of polysilicon shield on spiral inductors for silicon-based RF IC's

Increasing demands for more affordable personal mobile communication equipment have motivated research and development of low cost, high performance silicon-based on-chip inductors. Current silicon technology uses a conductive substrate, which causes unwanted energy dissipation. Inserting a patterned polysilicon shield beneath inductors can help reduce this substrate loss. Effects of the polysilicon ground shield on inductor performance have been investigated. An inductor utilizing a new high resistivity polysilicon floating shield is shown in this paper to have improved inductive characteristics.

A New Millimeter-Wave Fixture Deembedding Method Based on Generalized Cascade Network Model

In this letter, a universal cascade-based deembedding technique was presented for on-wafer characterization of the RF CMOS device. As compared with existing deembedding approaches, it is developed based on unique combinations of two THRU structures that enable efficient deembedding of fixture parasitics without any inaccurate lumped approximation or requirement of known standards. The proposed deembedding technique is validated on 0.13- μm CMOS devices and has been proven to be more accurate than existing lumped and cascade-based deembedding techniques. As a result, it gives deeper physical prediction on transistor gate capacitances and transconductance. Therefore, it is highly suitable to be applied for device characterization at millimeter-wave frequencies.

An Accurate Two-Port De-Embedding Technique for RF/Millimeter-Wave Noise Characterization and Modeling of Deep Submicrometer Transistors

An accurate and simple noise de-embedding technique is proposed for high-frequency noise characterization of transistors. It is demonstrated on 0.13-μm CMOS devices for up to 80 GHz. The proposed technique adopts a generalized two-port fixture model in conjunction with a set of shielded based structures, which enable simple de-embedding of fixture parasitic for up to the Metal 1 level. Unlike other methods, it is capable of simultaneously accounting for the parasitic effects of probe to pad contact impedances and metal finger parasitic while using only three dummy test structures. Also, it is designed to accommodate nonsymmetry between bond pad parasitic elements at two-port without consuming additional silicon area. This corresponds to a reduction in noise de-embedding error, which increases along the frequency domain (6% of NFmin at 80 GHz). Meanwhile, underestimation of metal finger parasitic by conventional techniques has lead to degradation in noise performance (NFmin) of 0.13-μm CMOS transistors by more than 3.5 dB at 80 GHz. Further validation results from extracted gate capacitance and transistor gain performance provide solid support to the proposed de-embedding technique.

An area efficient high turn ratio monolithic transformer for silicon RFIC

A novel way of manufacturing an on-chip transformer that produces high inductance ratio (LSec/LPri > 30) with excellent area efficiency is presented. This technique uses an electrical all-round coupling effect of a conductor A (primary coil), having large effective width, and a densely routed conductor B (secondary coil). Thus, a high turn ratio monolithic transformer, using minimum die size, is realizable on silicon. The coil having the dense routing can also be doubled up as a monolithic RF choke on silicon. In this work, area efficiency is compared between various type of existing transformer structures (i.e. interleaved and stacked transformer), based on unit inductance. The method presented is fully compatible to all the foundry standard CMOS processes.

THRU-Based Cascade De-embedding Technique for On-Wafer Characterization of RF CMOS Devices

In this paper, an accurate two-port cascade-based de-embedding technique is presented for characterization of RF devices. It uses two and four structures for device structure with symmetrical and asymmetrical layouts, respectively. Specifically, it outperforms the existing de-embedding techniques by showing distinct capability of accounting for both series contact resistance and distributed effects of interconnects. Furthermore, it is designed to overcome the deficiency of existing transmission line-based techniques in dealing with the interconnects of nonuniform line width. To avoid over de-embedding errors in lumped techniques, the deembedding is performed in unique steps with solely THRU structures for better prediction of test fixture parasitic. The proposed technique is verified on THRU line for a wide frequency range from 2 to 50 GHz. It demonstrates better performance over existing transmission line-based technique as evidenced by excellent agreement with electromagnetic simulation result of THRU line. This is further confirmed by validation result on deembedded gain and gate capacitance of 0.13-μm nMOS devices.

Substrate-Induced Noise Model and Parameter Extraction for High-Frequency Noise Modeling of Sub-Micron MOSFETs

In this paper, a substrate-induced drain-current noise model is developed in addition to the channel thermal noise to explain the non-white-noise characteristic found in the measured drain-current noise in the gigahertz range. The substrate-induced drain-current noise model is derived from the proposed small-signal equivalent circuit with a substrate coupling network and a substrate thermal noise source. The model parameter extraction method utilizing Y-parameter analysis on the proposed small-signal equivalent circuit is demonstrated. The model for the total drain-current noise, the gate-current noise, their cross-correlation, and thereafter the four noise parameters is presented and verified experimentally. Excellent agreement between simulated and measured noise data has been obtained over different dimensions and operating conditions.

Enabling wireless communications with state-of-the-art RF CMOS and SiGe BiCMOS technologies

The choice of technology for todays mixed-signal/RF system-on-chip (SOC) designs has been driven by the performance enhancements and cost advantage derived from scaled CMOS technologies. This paper discusses the performance improvements of RF transistors resulting from technology downscaling. Comparisons between scaled RF CMOS and SiGe BiCMOS technologies to highlight the benefits of employing SiGe HBT devices in certain applications are made. Other technology enablements discussed include accurate, scalable models and statistical models to address the need for design flexibility and robust manufacturing. Thereafter the introduction of high Q inductors, high density capacitors and varactors as basic passive components for RF circuits are discussed. Analog requirements such as mismatch, temperature linearity and voltage linearity are also discussed.

Extremely high-Q stacked transformer-type inductors for RF applications

A stacked tunable inductor with extremely high quality factor (Q) (>2000) is presented. Compared with transformer-type inductors with interleaved configuration, full-wave electromagnetic (EM) simulation results demonstrate that the stacked structure offers greater advantages in terms of area efficiency, achievable inductance value, and peak Q frequency. Besides, detailed discussions on power levels at the inputs of driving coils are presented to illustrate the effects of parasitic capacitance between the primary coil and driving coil.