Josef Schnell

Data strobe synchronization for DRAM devices

Integrated circuit chip having a first delay circuit trimmed via a second delay circuit

DELAY LOCK LOOP AND UPDATE METHOD WITH LIMITED DRIFT AND IMPROVED POWER SAVINGS

DLL lock scheme with multiple phase detection

Write burst stop function in low power DDR sDRAM

Voltage detection circuit and internal voltage clamp circuit

Memory having status register read function

Method and apparatus for temperature compensating off chip driver (OCD) circuit

Vertically-Folded Bitline Architecture

Edge pad architecture for semiconductor memory