Joseph N. Kozhaya

Power supply noise aware workload assignment for multi-core systems

As the industry moves from single- to multi-core processors, the challenges of how to reliably design and analyze power delivery for such systems also arise. We study various workload assignments to cores and their impact on the global power grid noise. We develop metrics to estimate the amount of noise propagated from core to core and propose a power supply noise aware workload assignment method. In our experiments, we show that performance loss can be significant if workload assignment is not properly made.

ESD design automation for a 90nm ASIC design system

Design tools for ESD are described that ensure robust protection at both the cell and chip level in a high-volume, highly automated ASIC design system. There are three primary components: Design Rule Checking (DRC) for ESD; transient CDM simulations on extracted netlists; and analysis of chip-level power supply net resistances.

PACMAN: Driving Nonuniform Clock Grid Loads for low-skew robust clock network

Clock grid is a mainstream clock network methodology for high performance microprocessor and SOC designs. Clock skew, power usage and robustness to PVT (power, voltage, temperature) are all important metrics for a high quality clock grid design. Tree-driven-grid clock network is a typical clock grid clock network. It includes a clock source, a buffered tree, leaf buffers, a mesh clock grid, local clock buffers, and latches as shown in Fig. 1. For such network, one big challenge is how to connect the leaf level buffers of the global tree to the grid with nonuniform loads under tight slew and skew constraints. The choice of tapping points that connect the leaf buffers to the clock grid are critical to the quality of the clock designs. Good tapping points can minimize the clock skew and reduce power. In this paper, we proposed a new algorithm to select the tapping points to build the global tree as regular and symmetric as possible. From our experimental results, the proposed algorithm can efficiently reduce global clock skew, rising slew, maximum overshoot, reduce power, and avoid local skew violation.Clock grid is a mainstream clock network methodology for high performance microprocessor and SOC designs. Clock skew, power usage and robustness to PVT (power, voltage, temperature) are all important metrics for a high quality clock grid design. Tree-driven-grid clock network is a typical clock grid clock network. It includes a clock source, a buffered tree, leaf buffers, a mesh clock grid, local clock buffers, and latches as shown in Fig. 1. For such network, one big challenge is how to connect the leaf level buffers of the global tree to the grid with nonuniform loads under tight slew and skew constraints. The choice of tapping points that connect the leaf buffers to the clock grid are critical to the quality of the clock designs. Good tapping points can minimize the clock skew and reduce power. In this paper, we proposed a new algorithm to select the tapping points to build the global tree as regular and symmetric as possible. From our experimental results, the proposed algorithm can efficiently reduce global clock skew, rising slew, maximum overshoot, reduce power, and avoid local skew violation.

Myth busters: microprocessor clocking is from Mars, ASICs clocking is from Venus

This paper compares and contrasts two common clock distribution styles: clock grids, the preferred microprocessor distribution style, and clock trees, the preferred ASICs distribution style. After a high level description of the routing methodologies for clock grids and clock trees, a case study is presented to compare the performance and cost trade-off of grids and trees. Our results show that clock grids consume more power and wiring resources but only to achieve aggressive clock targets. In this example a clock tree style uses 28% less wiring than a full clock grid style but suffers 12 ps more skew. However, compared to a sparse grid style, a clock tree solution uses only 4% less wiring and suffers 9.6 ps higher skew. The key message is that the cost in extra wiring and power consumption across different clock distribution styles is mainly driven by performance targets as opposed to being fundamentally dictated by the grid vs. tree decision.

Power network analysis for ESD robustness in a 90nm ASIC design system

ALSIM-ESD is a design automation tool to analyze power networks for good ESD performance in a high-volume, highly automated ASIC design system. The tool calculates the voltage drop produced in the power network by an ESD discharge and checks that it remains below circuit failure voltages. Automatic fix-up operations are provided to correct excessive resistance in the ESD discharge path.