Phillip J. Restle

SiGe-channel heterojunction p-MOSFET's

The advances in the growth of pseudomorphic silicon-germanium epitaxial layers combined with the strong need for high-speed complementary circuits have led to increased interest in silicon-based heterojunction field-effect transistors. Metal-oxide-semiconductor field-effect transistors (MOSFETs) with SiGe channels are guided by different design rules than state-of-the-art silicon MOSFETs. The selection of the transistor gate material, the optimization of the silicon-germanium channel profile, the method of threshold voltage adjustment, and the silicon-cap and gate-oxide thickness sensitivities are the critical design parameters for the p-channel SiGe MOSFET. Two-dimensional numerical modeling demonstrates that n/sup +/ polysilicon-gate SiGe p-MOSFETs have acceptable short-channel behavior at 0.20 /spl mu/m channel lengths and are preferable to p/sup +/ polysilicon-gate p-MOSFETs for 2.5 V operation. Experimental results of n/sup +/-gate modulation-doped SiGe p-MOSFETs illustrate the importance of the optimization of the SiGe-channel profile. When a graded SiGe channel is used, hole mobilities as high as 220 cm/sup 2//V.s at 300 K and 980 cm/sup 2//V.s at 82 K are obtained. >

On-chip wiring design challenges for gigahertz operation

This paper reviews the status of present day on-chip wiring design methodologies and understanding. A brief explanation is given of the fundamental transmission-line properties that should be considered for accurate prediction of crosstalk, common-mode noise and clock skew. The deficiencies of RC-circuit representation are highlighted and design guidelines are given for using modeling and simulation techniques that have been previously used for package interconnections. Such techniques are believed to teach designers how to make better use of available technologies and help them architect systems that operate with many-GHz clock rates.

A new 'shift and ratio' method for MOSFET channel-length extraction

A shift-and-ratio method for extracting MOSFET channel length is presented. In this method, channel mobility can be any function of gate voltage, and high source-drain resistance does not affect extraction results. It is shown to yield more accurate and consistent channel lengths for deep-submicrometer CMOS devices at room and low temperatures. It is also found that, for both nFET and pFET, the source-drain resistance is essentially independent of temperature from 300 to 77 K.<<ETX>>

The circuit and physical design of the POWER4 microprocessor

The IBM POWER4 processor is a 174-milliontransistor chip that runs at a clock frequency of greater than 1.3 GHz. It contains two microprocessor cores, high-speed buses, and an on-chip memory subsystem. The complexity and size of POWER4, together with its high operating frequency, presented a number of significant challenges for its multisite design team. This paper describes the circuit and physical design of POWER4 and gives results that were achieved. Emphasis is placed on aspects of the design methodology, clock distribution, circuits, power, integration, and timing that enabled the design team to meet the project goals and to complete the design on schedule.

Designing the best clock distribution network

Clock distribution has become an increasingly challenging problem for VLSI designs, consuming an increasing fraction of resources such as wiring, power, and design time. Unwanted differences or uncertainties in clock network delays degrade performance or cause functional errors. Three dramatically different strategies being used in the VLSI industry to address these challenges are compared. Novel modeling and measurement techniques are used to investigate on-chip transmission-line effects that are important for high performance clock distribution networks.

High-mobility modulation-doped SiGe-channel p-MOSFETs

A novel subsurface SiGe-channel p-MOSFET is demonstrated in which modulation doping is used to control the threshold voltage without degrading the channel mobility. A novel device design consisting of a graded SiGe channel, an n/sup +/ polysilicon gate, and p/sup +/ modulation doping is used. A boron-doped layer is located underneath the graded and undoped SiGe channel to minimize process sensitivity and maximize transconductance. Low-field hole mobilities of 220 cm/sup 2//V-s at 300 K and 980 cm/sup 2//V-s at 82 K were achieved in functional submicrometer p-MOSFETs.<<ETX>>

Full-wave PEEC time-domain method for the modeling of on-chip interconnects

With the advances in the speed of high-performance chips, inductance effects in some on-chip interconnects have become significant. Specific networks such as clock distributions and other highly optimized circuits are especially impacted by inductance. Several difficult aspects have to be overcome to obtain valid waveforms for problems where inductances contribute significantly. Mainly, the geometries are very complex and the interactions between the capacitive and inductive currents have to be taken into account simultaneously. In this paper, we show that a full-wave partial element equivalent circuit method, which includes the delays among the partial elements, leads to an efficient solver enabling the analysis of large meaningful problems. Applying this method to several examples leads to helpful insights for realistic very large scale integration wiring problems. It is shown in this paper that the impact overshoot, reflections, and inductive coupling are critical for the design of critical on-chip interconnects.

Uniform-phase uniform-amplitude resonant-load global clock distributions

This work presents a new approach to global clock distribution in which tree-driven grids are augmented with on-chip spiral inductors to resonate the clock capacitance. In this scheme, the energy of the fundamental frequency resonates between electric and magnetic forms, with the reduced admittance of the clock network allowing for significantly lower gain requirements in the buffering network. The substantial improvements in jitter and power resulting from this approach are presented using measurement results from two test chips, one fabricated in a 90-nm and the other in a 0.18-/spl mu/m CMOS technology.

Design of resonant global clock distributions

We present a new approach to global clock distribution in which traditional tree-driven grids are augmented with on-chip inductors to resonate the clock capacitance at the fundamental frequency of the clock node. Rather than being dissipated as heat, the energy of the fundamental resonates between electric and magnetic forms. The clock drivers must only provide the energy necessary to overcome losses. As a result, power reduction of over 80% is possible depending on the Q of the resonant system. Clock latency is also improved because the effective capacitance of the grid is lower, and fewer buffer stages are necessary to drive the grid. Skew and jitter reductions come about because of this reduced buffer latency.

The clock distribution of the POWER4 microprocessor

The clock distribution on the Power4 dual-processor chip supplies a single critical 1.5 GHz clock from one SOI-optimized PLL to 15,200 pins on a large chip with 20 ps skew and 35 ps jitter. The network contains 64 tuned trees driving a single grid, and specialized tools to achieve targets on schedule with no adjustment circuitry.