Andrzej J. Strojwas

Exploring regular fabrics to optimize the performance-cost trade-off

While advances in semiconductor technologies have pushed achievable scale and performance to phenomenal limits for ICs, nanoscale physical realities dictate IC production based on what we can afford. We believe that IC design and manufacturing can be made more affordable, and reliable, by removing some design and implementation flexibility and enforcing new forms of design regularity. This paper discusses some of the trade-offs to consider for determination of how much regularity a particular IC or application can afford. A Via Patterned Gate Array is proposed as one such example that trades performance for cost by way of new forms of design regularity.

Design methodology for IC manufacturability based on regular logic-bricks

Implementing logic blocks in an integrated circuit in terms of repeating or regular geometry patterns (Palusinski et al., 2001 and Strojwas, 2003) can provide significant advantages in terms of manufacturability and design cost (Pileggi et al., 2003). Various forms of gate and logic arrays have been recently proposed that can offer such pattern regularity to reduce design risk and costs. In this paper, we propose a full-mask-set design methodology which provides the same physical design coherence as a configurable array, but with area and other design benefits comparable to standard cell ASICs. This methodology is based on a set of simple logic primitives that are mapped to a set of logic bricks that are defined by a restrictive set of RET (resolution enhancement technique)-friendly geometry patterns. We propose a design methodology to explore trade-offs between the number of bricks and associated level of configurability versus the required silicon area. Results are shown to compare a design implemented with a small number of regular bricks to an implementation based on a full standard cell library in a 90nm CMOS technology.

Congestion-Aware Logic Synthesis

In this era of Deep Sub-Micron (DSM) technologies, the impact of interconnects is becoming increasingly important as it relates to integrated circuit (IC) functionality and performance. In the traditional top-down IC design flow, interconnect effects are first taken into account during logic synthesis by way of wireload models. However, for technologies of 0.25 /spl mu/m and below, the wiring capacitance dominates the gate capacitance and the delay estimation based on fanout and design legacy statistics can be highly inaccurate. In addition, logic block size is no longer dictated solely by total cell area, and is often limited by wiring area resources. For these reasons, wiring congestion is an extremely important design factor, and should be taken into consideration at the earliest possible stages of the design flow. In this paper we propose a novel methodology to incorporate congestion minimization within logic synthesis, and present results for industrial circuits that validate our approach.

Routing architecture exploration for regular fabrics

In an effort to control the parameter variations and systematic yield problems that threaten the affordability of application-specific ICs, new forms of design regularity and structure have been proposed. For example, there has been speculation [6] that regular logic fabrics [1] based on regular geometry patterns [2] can offer tighter control of variations and greater control of systematic manufacturing failures. In this paper we describe a routing framework that accommodates arbitrary descriptions of regular and structured routing architectures. We further propose new regular routing architectures and explore the various performance vs. manufacturability trade-offs. Results demonstrate that a more regular, restricted routing architecture can provide a substantial advantage in terms of manufacturability and predictability while incurring a moderate performance penalty.

Correlation-aware statistical timing analysis with non-gaussian delay distributions

Process variations have a growing impact on circuit performance for todays integrated circuit (IC) technologies. The non-Gaussian delay distributions as well as the correlations among delays make statistical timing analysis more challenging than ever. In this paper, the authors presented an efficient block-based statistical timing analysis approach with linear complexity with respect to the circuit size, which can accurately predict non-Gaussian delay distributions from realistic nonlinear gate and interconnect delay models. This approach accounts for all correlations, from manufacturing process dependence, to re-convergent circuit paths to produce more accurate statistical timing predictions. With this approach, circuit designers can have increased confidence in the variation estimates, at a low additional computation cost.

Understanding and addressing the impact of wiring congestion during technology mapping

Traditionally, interconnect effects are taken into account duringlogic synthesis via wireload models, but their ineffectiveness forDSM technologies has been demonstrated and various physicalsynthesis approaches have been spawned to address the problem. Ofparticular interest is that logic block size is no longer dictatedexclusively by total cell area, yet synthesis optimizationobjectives are aimed specifically at minimizing the number and sizeof cells. Methodologies that incorporate congestion within thelogic synthesis objective function have been proposed in[9][10][11] and [15]; however, as we will demonstrate, predictingthe true congestion prior to layout is not possible, and theefficacy of any approach can only be evaluated after routing iscompleted within the fixed die size. In this paper we propose apractical, complete methodology which first performscongestion-aware technology mapping using a global weighting factorfor the cost function [15], and then applies incremental localizedunmapping and remapping on congested areas. This complete approachaddresses the problem that one global factor is not ideally suitedfor all regions of the designs. Most importantly, through theapplication of this methodology to industrial examples we will showthat any attempt at a purely top-down single-pass congestion-awaretechnology mapping is merely wishful thinking.

Model order-reduction of RC(L) interconnect including variational analysis

As interconnect feature sizes continue to scale to smaller dimensions, long interconnect can dominate the IC timing performance, but the interconnect parameter variations make it difficult to predict these dominant delay extremes. This paper presents a model order-reduction technique for RLC interconnect circuits that includes variational analysis to capture manufacturing variations. Matrix perturbation theory is combined with dominant-pole-analysis and Krylov-subspace-analysis methods to produce reduced-order models with direct inclusion of statistically independent manufacturing variations. The accuracy of the resulting variational reduced-order models is demonstrated on several industrial examples.

Impact of interconnect variations on the clock skew of a gigahertz microprocessort

Due to the large die sizes and tight relative clock skew margins, the impact of interconnect manufacturing variations on the clock skew in todays gigahertz microprocessors can no longer be ignored. Unlike manufacturing variations in the devices, the impact of the interconnect manufacturing variations on IC timing performance cannot be captured by worst/best case corner point methods. Thus it is difficult to estimate the clock skew variability due to interconnect variations. In this paper we analyze the timing impact of several key statistically independent interconnect variations in a context-dependent manner by applying a previously reported interconnect variational order-reduction technique. The results show that the interconnect variations can cause up to 25% clock skew variability in a modern microprocessor design.

Statistical Simulation of the IC Manufacturing Process

Information about the random behavior of the IC manufacturing process can be applied for IC and process design tasks. In this paper a methodology for modeling random fluctuations of IC manufacturing process is proposed. A simulator of a complete bipolar manufacturing process called FABRICS, is described. A few applications illustrating advantages of the proposed statistical process modeling method are discussed.

In-line defect sampling methodology in yield management: an integrated framework

In this paper we provide an integrated framework for designing the optimal defect sampling strategy for wafer inspection, which is crucial in yield management of state-of-the-art technologies. We present a comprehensive cost-based methodology which allows us to achieve the trade-off between the cost of inspection and the cost of yield impact of the undetected defects. We illustrate the effectiveness of our methodology using data from several leading fablines across the world. We demonstrate that this work has already caused a significant change in the sampling practices in these fablines especially in the area of defect data preprocessing (declustering), in-line defect based yield prediction, and optimization of wafer inspection equipment allocation.