Jouni Tomberg

Fully digital neural network implementation based on pulse density modulation

An efficient implementation of a Hopfield-type fully connected neural-network architecture is presented that is based on a pulse-density modulation technique implemented by using fully digital structures. The synaptic weights are programmable, and thus the area of one synapse and the entire network depends on the resolution of the weight. Advantages of the design are its modularity and expandability

Signal processing requirements in pan-European digital mobile communications

The authors give an overview of the basic functions and techniques of the user equipment of the proposed pan-European digital communications system. The multipath equalizer and channel decoder of the receiver together with the speech codec are identified to be the most complicated devices from the viewpoint of signal processing and integration. Three different approaches for implementation, using general-purpose digital signal processing (DSPs), application-oriented DSPs, and dedicated full custom VLSI, are discussed. With particular reference to the speech codec, a detailed analysis of the full-custom VLSI implementation is made and the results are compared with the other approaches. It is concluded that even though the full-custom approach offers considerable benefits in terms of power consumption and use of silicon area, other matters such as flexibility in operation and further development also have to be taken into account.<<ETX>>

VLSI implementation of pulse density modulated neural network structure

An efficient implementation of a Hopfield-type, fully connected neural-network architecture is presented. It is based on a pulse-density-modulation technique implemented using switched-capacitor structures. The synaptic weights are programmable, and thus the area of one synapse and the entire network depends on the resolution of the weight. Advantages of the design are simple synapse structure and thus small area, expandability, and modularity.<<ETX>>

An effective training method for fully digital pulse-density modulated neural network architecture

An effective training method for on-chip learning in a fully connected synchronous pulse-density modulated neural network architecture is presented. The pulse-density modulation technique and fully digital implementation offer expandable VLSI implementation with completely stand-alone operation capability. The communication with the host processor is done via buffer memory. Applications can be found in pattern recognition.<<ETX>>

VLSI Architecture of the Boltzmann Machine Algorithm

A new efficient programmable implementation of Boltzmann Machine algorithm will be presented. It is based on pulse-density modulation technique. Advantages of the design are simple structure of a synapse and thus small area, modularity and expandability. Furthermore, these structures can be used for various other neural network architectures. Applications for this type of networks can be found in the area of pattern recognition, image restauration and various optimization tasks.

Parallel coprocessor for Kohonen's self-organizing neural network

A new efficient integrated circuit implementation of the Self-Organising Feature Map algorithm is described. The fully digital hardware is designed for high speed parallel processing and modular expandability. The hardware implementation acts as a neural coprocessor which uses synchronous, bit-serial arithmetic. It includes functional units which perform the Euclidean distance computation, the minimum distance search, the memory controlling, and the updating function. The on-chip learning facilitates fully autonomous operation.<<ETX>>

Configurable sparse distributed memory hardware implementation

A configurable hardware implementation of Kanervas Sparse Distributed Memory has been developed using advanced structures. The system consists of the host computer, address unit and memory unit. The address and memory units have been implemented with commercially available components to two functioning boards, and they perform the Hamming distance comparison and memory storage functions. In order to achieve effective hardware realization the units are designed for highly parallel processing. The host computer is used to edit, compile, and down-load the programs to be run in the units. The performance estimations are also presented.<<ETX>>

SOME IC IMPLEMENTATIONS OF ARTIFICIAL NEURAL NETWORKS USING SYNCHRONOUS PULSE-DENSITY MODULATION TECHNIQUE

Pulse-density modulation technique offers a very effective and robust method to implement artificial neural network structures, because it mimics some biological features of neuron action. In this paper various Integrated Circuit (IC) implementations based on the pulse-density modulation technique are explored. Two different approaches has been used: analog switched-capacitor structures and fully digital structures. These structures can be used in both Hopfield-type networks and more complicated Boltzmann-machine as well as other algorithms.

VLSI ARCHITECTURE OF THE SELF-ORGANIZING NEURAL NETWORK USING SYNCHRONOUS PULSE-DENSITY MODULATION TECHNIQUE

- A new efficient single-chip integrated circuit architecture of self-organizing neural network algorithm with on-chip learning property has been designed. The design is based on the pulse-density modulation technique.

Synchronous Pulse Density Modulation in Neural Network Implementation

Artificial neural networks (ANN) are massively parallel, distributed information processing structures [Wasserman 89]. They consist of huge amount of processing elements interconnected via weighted connections. The idea for these networks is based on the biological world, but their models are considerable simpler. According to the biological models the processing elements are called “neurons” and the weighted connections “synapses”. The signal lines from neurons to synapses and from synapses to neurons are called “axons” and “dendrites”, respectively. Although the structure of neurons and synaptic connections is relatively simple, the large amount of them needed for practical applications makes the implementation of ANNs quite complicated. One effective way to implement ANNs is VLSI circuits. In the simplest case a neuron can be modeled by nonlinear summing amplifier. The weight values of the synaptic connections, which are responsible for information storage, can be implemented by resistors of different strengths. The learning process changes these weight values according to some specified rule. From the information processing point of view a synapse can be considered as a multiplier which does the product of the incoming neuron value with the stored weight value. A neuron then adds together the output values of the synapses and performs a nonlinear function for the resulting sum. Because of wide range of different ANN algorithms we often need slightly more complicated neuron structure and the strength of the synaptic connections must be easily programmable.