Tapani Ritoniemi

Design of stable high order 1-bit sigma-delta modulators

A method for designing stable 1-b high-order (>or=3) sigma-delta modulators is presented. The stability analysis is based on the root locus and modeling the quantizer for each clock period at a time. The quantizers gain in the modulator at the present clock period determines the modulators stability for the next clock period. If the modulator is stable during each clock period, it is unconditionally stable and behaves as a linear analog/digital converter. Examples with third-, fourth-, fifth-, and sixth-order sigma-delta modulators are given to explore the use of the proposed method in practice. With the designed sixth-order modulator it is possible to achieve 23-b signal-to-quantization noise ratio at the oversampling ratio of 64.<<ETX>>

An oversampled sigma-delta A/D converter circuit using two-stage fourth order modulator

A sigma-delta analog/digital (A/D) converter realization using a two-stage fourth-order modulator architecture and a fifth-order digital running-sum decimation filter is presented. The analog part of the converter consists of two cascaded second-order modulators. Scaling is used between the sections in order to achieve the modest requirements for component matching and the integrators gain and phase. A digital running-sum filter is used for the decimation to 4f/sub s/ or 2f/sub s/. A dedicated seven-instruction filter processor is designed to perform the final decimation and I/O-communication. The whole system operates on a single 5-V operation voltage.<<ETX>>

Multiplier-free decimator algorithms for superresolution oversampled converters

A class of efficient linear-phase finite impulse response (FIR) decimators for attenuating the out-of-band noise generated by a high-order sigma-delta analog-to-digital modular is introduced. The stopband attenuation of these decimators is more than 120 dB. The decimators contain no general multipliers and a few data memory locations, thereby making them easily VLSI-realizable. This is achieved by using several decimation stages, with each stage containing a small number of delays and arithmetic operations. Some of the stages are constructed using low-order building blocks which are combined to give a selective filter using a few additional tap coefficients and adders. The output sampling rate of these decimators is the minimum possible one, and the proposed decimators can be used, with very slight changes, for many oversampling ratios. These decimators highly attenuate the undesired out-of-band signal components of the input signal, thus significantly relaxing the antialiasing prefilter requirements.<<ETX>>

Fully digital neural network implementation based on pulse density modulation

An efficient implementation of a Hopfield-type fully connected neural-network architecture is presented that is based on a pulse-density modulation technique implemented by using fully digital structures. The synaptic weights are programmable, and thus the area of one synapse and the entire network depends on the resolution of the weight. Advantages of the design are its modularity and expandability

Fully differential CMOS sigma-delta modulator for high performance analog-to-digital conversion with 5 V operating voltage

The authors present a high-performance second-order sigma-delta modulator for modem and ISDN (integrated-services digital network) analog-to-digital (A/D) conversion applications. The major performance design limiting factors are demonstrated. It is shown that a true 16-bit A/D converter with single 5-V power supply for voice band can be realized with an oversampling ratio of 512; and a 16-bit dynamic range is achieved with an oversampling ratio of 256. The die size of the proposed modulator, using 2.5- mu m CMOS technology, is only 0.56 mm/sup 2/.<<ETX>>

Direct conversion using lowpass sigma-delta modulation

A method for quadrature demodulation by subsampling with sigma-delta analog-to-digital converters is discussed, and a correlator receiver structure based on this method is described. The almost completely digital demodulator structure is based on second-order sampling and sigma-delta analog-to-digital converters. A theoretical performance analysis is presented, and a measurement system for the method is described. The proposed structure can be implemented on a single integrated circuit.<<ETX>>

VLSI-realizable multiplier-free interpolators for high-order sigma-delta D/A converters

A class of efficient linear-phase FIR interpolators for superresolution sigma-delta digital-to-analog (D/A) converters are introduced. These interpolators contain no general multipliers and very few data memory locations, thereby making them easily VLSI-realizable. This is achieved by using several interpolation stages with each stage containing a small number of delays and arithmetic operations. The proposed interpolators can be used, with very slight changes, for many interpolation ratios. As an example, an interpolator is designed for a 20-b overall performance in the case of a fifth-order noise shaper.<<ETX>>

Second-order sampling and oversampled A/D- and D/A-converters in digital data transmission

Basic structures for transmitting and receiving any quadrature modulated signal have been developed. As an example, the structures were applied to MSK modulation, and this resulted in working MSK modulator and demodulator structures that were verified by simulations at the functional level. A very simple and compact digital VLSI implementation of a MSK modulator can be built using the structure. The only analog part is the bandpass filter, which is also required in the conventional modulator structure. The use of sigma-delta A/D-convertors makes the demodulator structure very robust. The highest clock frequency (four times the carrier frequency f/sub c/) is needed only for synchronizing purposes, and the parts would be clocked at f/sub c/.<<ETX>>

VLSI implementation of pulse density modulated neural network structure

An efficient implementation of a Hopfield-type, fully connected neural-network architecture is presented. It is based on a pulse-density-modulation technique implemented using switched-capacitor structures. The synaptic weights are programmable, and thus the area of one synapse and the entire network depends on the resolution of the weight. Advantages of the design are simple synapse structure and thus small area, expandability, and modularity.<<ETX>>

A 50 MHz Cascaded Sigma-delta A/d Modulator

A high-performance cascaded sigma-delta modulator circuit with one-bit quantization is introduced. It has a fourth-order topology and provides functionally a 16-bit signal-to-quantization noise with an oaersampling ra- tio of 32. Two modulator circuits have been designed to compare switched-capacitor integrator amplifier structures. One version uses a new dynamically biased class A/B am- plifier topology and the other one is a conventional folded cascade OTA. The prototype was fabricated using a 1.2 mi- cron CMOS technology and it achieves 9 eflective bits with 50 MHz sampling rate.