Ju Shen

Programmable gate array with improved interconnect structure, input/output structure and configurable logic block

Programmable gate array with improved interconnect structure

Programmable gate array device having cascaded means for function definition

Programmable gate array with improved configurable logic block

Array of configurable logic blocks including cascadable lookup tables

Configurable logic array including IOB to longlines interconnect means for providing selectable access to plural longlines from each IOB (input/output block)

Constant delay interconnect for coupling configurable logic blocks

Array of configurable logic blocks including network means for broadcasting clock signals to different pluralities of logic blocks

Array of configurable logic blocks each including a first lookup table output coupled to selectively replace an output of second lookup with an alternate function output

Improved programmable gate array