Ju Shen | Researchain

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Publication

Featured researches published by Ju Shen.

Archive | 1993

Programmable gate array with improved interconnect structure, input/output structure and configurable logic block

Om P. Agrawal; Michael J. Wright; Ju Shen

Archive | 1989

Programmable gate array with improved interconnect structure

Om P. Agrawal; Michael J. Wright; Ju Shen

Archive | 1994

Programmable gate array device having cascaded means for function definition

Om P. Agrawal; Michael J. Wright; Ju Shen

Archive | 1989

Programmable gate array with improved configurable logic block

Om P. Agrawal; Michael J. Wright; Ju Shen

Archive | 1995

Array of configurable logic blocks including cascadable lookup tables

Om P. Agrawal; Michael J. Wright; Ju Shen

Archive | 1998

Configurable logic array including IOB to longlines interconnect means for providing selectable access to plural longlines from each IOB (input/output block)

Om P. Agrawal; Michael J. Wright; Ju Shen

Archive | 1995

Constant delay interconnect for coupling configurable logic blocks

Om P. Agrawal; Michael J. Wright; Ju Shen

Archive | 1996

Array of configurable logic blocks including network means for broadcasting clock signals to different pluralities of logic blocks

Om P. Agrawal; Michael J. Wright; Ju Shen

Archive | 1995

Array of configurable logic blocks each including a first lookup table output coupled to selectively replace an output of second lookup with an alternate function output

Om P. Agrawal; Michael J. Wright; Ju Shen

Archive | 1990

Improved programmable gate array

Om P. Agrawal; Michael J. Wright; Ju Shen

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Collaboration

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Top Co-Authors

Michael J. Wright

Advanced Micro Devices

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Top Co-Authors

Om P. Agrawal

Advanced Micro Devices

View shared research outputs

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Archive Network Publication Hotspot Collaboration

Network

Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot

Dive into the research topics where Ju Shen is active.

Publication

Featured researches published by Ju Shen.

Programmable gate array with improved interconnect structure, input/output structure and configurable logic block

Programmable gate array with improved interconnect structure

Programmable gate array device having cascaded means for function definition

Programmable gate array with improved configurable logic block

Array of configurable logic blocks including cascadable lookup tables

Configurable logic array including IOB to longlines interconnect means for providing selectable access to plural longlines from each IOB (input/output block)

Constant delay interconnect for coupling configurable logic blocks

Array of configurable logic blocks including network means for broadcasting clock signals to different pluralities of logic blocks

Array of configurable logic blocks each including a first lookup table output coupled to selectively replace an output of second lookup with an alternate function output

Improved programmable gate array

Collaboration

Dive into the Ju Shen's collaboration.