Ju-youn Kim

Novel Enhanced Stressor with Graded Embedded SiGe Source/Drain for High Performance CMOS Devices

We present an advanced CMOS integration scheme based on embedded SiGe (eSiGe) with a novel graded germanium process. The retention of channel strain enabled a pFET performance gain of 15% over a non-graded eSiGe control. When combined with a compressive stress liner (CSL), the pFET drive current reached 770muA/mum at Ioff = 100nA/mum with VDD = 1V. Competitive nFET performance was maintained. Parasitics such as silicide and junction characteristics were not degraded

Study of vertical Si/SiO2 interface using laser-assisted atom probe tomography and transmission electron microscopy.

Laser-assisted atom probe tomography has opened the way to three-dimensional visualization of nanostructures. However, many questions related to the laser-matter interaction remain unresolved. We demonstrate that the interface reaction can be activated by laser-assisted field evaporation and affects the quantification of the interfacial composition. At a vertical interface between Si and SiO2, a SiO2 molecule tends to combine with a Si atom and evaporate as a SiO molecule, reducing the evaporation field. The features of the reaction depend on the direction of the laser illumination and the inner structure of tip. A high concentration of SiO is observed at a vertical interface between Si and SiO2 when the Si column is positioned at the center of the tip, whereas no significant SiO is detected when the SiO2 layer is at the center. The difference in the interfacial compositions of two samples was due to preferential evaporation of the Si layer. This was explained using transmission electron microscopy observations before and after atom probe experiments.

20nm DRAM: A new beginning of another revolution

For the first time, 20nm DRAM has been developed and fabricated successfully without extreme ultraviolet (EUV) lithography using the honeycomb structure (HCS) and the air-spacer technology. The cell capacitance (Cs) can be increased by 21% at the same cell size using a novel low-cost HCS technology with one argon fluoride immersion (ArF-i) lithography layer. The parasitic bit-line (BL) capacitance is reduced by 34% using an air-spacer technology whose breakdown voltage is 30% better than that of conventional technology.

Highly functional and reliable 8Mb STT-MRAM embedded in 28nm logic

We fabricated 8Mb 1T-1MTJ STT-MRAM macro embedded in 28nm CMOS logic platform by developing novel integration/stack/patterning technologies. MTJ memory cell array was successfully embedded into Cu backend without open fail and severe degradation of magnetic property. Advanced perpendicular MTJ stack using MgO/CoFeB was developed to show high TMR value of 180% after full integration. In addition, ion beam etching (IBE) process was optimized with power, angle, and pressure to reduce a short fail below 1 ppm. Through these novel technologies, we demonstrated highly functional and reliable 8Mb eMRAM macro having a wide sensing margin and strong retention property of 85 0C and 10yrs.

A 45nm Low Cost Low Power Platform by Using Integrated Dual-Stress-Liner Technology

Device performance has been boosted by integrating dual-stress-liners (DSL) in a 45nm low power platform as a cost effective approach. A stress-proximity-technique (SPT) has been explored to improve device performance without adding process complexity. Record drain currents of 840/490 muA/mum have been achieved for NMOS and PMOS, respectively, at 1.2V and off-leakage current of 1nA/mum. Junction profiles have been optimized to reduce the gate-induced-drain-leakage (GIDL). An asymmetric IO has been integrated into this low power technology for the first time, offering multiple advantages including low cost, performance gain up to 30% and reliability improvement as well

Considering physical mechanisms and geometry dependencies in 14nm FinFET circuit aging and product validations

We report the extensive 14nm FinFET reliability characterization work and provide physical mechanisms and geometry dependencies. BTI, HCI variability related to #of Fin used in design along with self-heat considerations are critical for product design and qualifications. We show that along with increased AFs and optimized product HTOL stress conditions, 5-10x more efficiency in time has been achieved. In addition, external mechanical strain on Fin reliability will be discussed.

A study of threshold switching of NbO2 using atom probe tomography and transmission electron microscopy.

Threshold switching is a phenomenon where the resistivity of an insulating material changes and the insulator exhibits metallic behavior. This could be explained by phase transformation in oxide materials; however, this behavior is also seen in amorphous insulators. In this study, through an ex-situ experiment using transmission electron microscopy (TEM), we proved that threshold switching of amorphous NbO2 accompanies local crystallization. The change in I-V characteristics after electroforming was examined by evaluating the concentration profile. Atom probe tomography (APT) combined with in-situ TEM probing technique was performed to understand the threshold switching in amorphous NbO2. The local crystallization in amorphous NbO2 was validated by the observed difference in time-of-flight (ToF) between amorphous and crystalline NbO2. We concluded that the slower ToF of amorphous NbO2 (a-NbO2) compared with crystalline NbO2 (c-NbO2) is due to the resistivity difference and trap-assisted recombination.

3D compositional characterization of Si/SiO2 vertical interface structure by atom probe tomography

Precise interpretation of three-dimensional atom probe tomography (3D-APT) data is necessary to reconstruct semiconductor-device structures. In particular, it is difficult to reconstruct the hetero-structure of conductors and insulators using APT analysis, due to the preferential evaporation of low-evaporation field-material. In this paper, shallow-trench isolation (STI) structure, consisting of a Si column and a SiO2 region, is analyzed using APT. The dimensional artifact known as the local-magnification-effect occurring as a result of the geometric deviation from the ideal hemisphere was successfully calibrated by ‘high-angle annular dark-field (HAADF) scanning transmission electron microscopy (STEM) tomography’ and Electron Energy Loss Spectroscopy (EELS). In the direction of the width, the Si layer was compressed by 50%, and the interface was expanded by 250% with respect to the reference data obtained for the same sample. A 5-nm-thick transition layer was observed at the interface between Si and SiO2. The composition of the transition layer follows the well-developed sequence Si-Si2O-SiO-SiO2 from the Si area to the SiO2 area. Atoms at the interface were likely to evaporate with a bit wider angle than atoms in the Si area due to the preferentially evaporated Si layer, which caused the interface area to appear locally magnified.

Mass Production Worthy MIM Capacitor On Gate polysilicon(MIM-COG) Structure using HfO 2 /HfO x C y N z /HfO 2 Dielectric for Analog/RF/Mixed Signal Application

We have successfully integrated a mass production worthy MIM capacitor on gate polysilicon (MIM-COG) structure using HfO₂/HfO_xC_yN_z/HfO₂(HNH) dielectric for the analog/RF/mixed signal application. The insertion of HfO_xC_yN_z into HfO₂ films can successfully suppress the crystallization. As a result, HNH film shows superior breakdown and VCC-a characteristics compared to HfO₂-AI₂O₃ multilayer stack. In addition, we suggest novel MIM-COG structure, which can solve metal routing issues in integration of conventional MIM capacitors. Also, by utilizing the MIM COG structure, the total number of mask can be reduced. Finally, MIM-COG structure with HNH dielectric shows high capacitance density (8.3fF/um²) and low VCC-a (700 ppm/V²). Moreover, excellent operation voltage for 10 year lifetime of MIM-COG structure with HNH (4.6 V) is achieved.

A high-density and low-cost self-aligned shallow trench isolation NOR flash technology with 0.14/spl mu/m/sup 2/ cell size

We have developed a new cell technology with extremely small cell size of 0.14 /spl mu/m/sup 2/ using 0.12 /spl mu/m process. The self-aligned shallow trench isolation (SA-STI) and self-aligned source (SAS) structure are adopted to minimize the cell size. To scale down the cell gate length and to improve the cell performance, high aspect-ratio floating gate and channel erasing scheme are used. Excellent endurance characteristics, tight threshold voltage distribution and good reliability have been verified in this work.