Juan Antonio Maestro

Improving Memory Reliability Against Soft Errors Using Block Parity

Memory reliability is an important issue. The continuous scaling of transistor technology enables the use of larger memories making soft errors more likely to occur. To ensure that those errors do not cause data corruption, error correcting codes (ECC) are commonly used. Single error correction-double error detection codes (SEC-DED) are typically implemented in each memory word, so that a single error in a word can be corrected and two errors can be detected. In this paper, a technique to improve the reliability of memories that use SEC-DED is studied. The proposed technique shows that it is possible to substantially improve the mean time to failure (MTTF) of the memory at the cost of increasing the access time for writing operations.

Error Detection Technique for a Median Filter

In digital image processing systems, the acquisition stage may capture impulsive noise along with the image. This physical phenomenon is commonly referred to as “salt-and-pepper” noise. The median filter is a nonlinear image processing operation used to remove this impulsive noise from images. This digital filter can be implemented in hardware to speed up the algorithm. However, an SRAM-based field-programmable gate array implementation of this filter is then susceptible to configuration memory bit flips induced by single event upsets, so a protection technique is needed for critical applications in which the proper filter operation must be ensured. In this paper, a fault-tolerant implementation of the median filter is presented and studied in-depth. Our protection technique checks if the median output is within a dynamic range created with the remaining nonmedian outputs. An output error signal is activated if a corrupted image pixel is detected, then a partial or complete reconfiguration can be performed to remove the configuration memory error. Experimental results show that our technique detects enough corrupted pixels in an image to prevent 91% of the corrupted images from being erroneously sent to the next image processing operation. This high error detection rate is achieved introducing only a 35% of additional resource overhead.

Characterizing a RISC-V SRAM-based FPGA implementation against Single Event Upsets using fault injection

Abstract The reliability of microprocessors is a big concern in space environments, where they are exposed to cosmic radiation. This radiation can produce Single Event Upsets (SEUs). Some of these microprocessors, often called soft processors, are implemented on SRAM-based FPGAs instead of being manufactured as an ASIC. Fault injection campaigns are needed in order to estimate the soft processor reliability in this harsh environment. This work, characterizes a new RISC soft-core, called lowRISC, based on the RISC-V ISA. Ten tests have been carried out to characterize the SEU sensitivity of lowRISC. Also, we have performed a comparison among lowRISC and other microprocessors, concluding that their sensitivities are all in the same range.

A method to recover critical bits under a double error in SEC-DED protected memories

Abstract Single Error Correction Double Error Detection (SEC-DED) codes are widely used to protect memories from soft errors due to their simple implementation. However, the limitation is that the double bit errors can just be detected but cannot be recovered by SEC-DED codes. In this paper, a method to recover some of the bits when a double error occurs is presented. This can be of interest for applications on which some bits store important information, for example control flags or the more significant bits of a value. For those, the proposed technique can in some cases determine whether those bits have been affected by the double error and when not, safely recover the correct values. However, the percentage of times that the bits can be recovered is small. The proposed scheme is also extended to increase this percentage by duplicating or triplicating the critical bits inside the word when there are spare bits. No modification to the decoding circuitry is needed, as the scheme can be implemented in the exception handler that is executed when a double error occurs. This facilitates the use of the proposed scheme in existing designs. Another option is to implement part of the scheme in hardware something that can be done with low cost.

A Scheme to Reduce the Number of Parity Check Bits in Orthogonal Latin Square Codes

The use of error-correcting codes is a common strategy to protect memories from errors. Single-error correction, double-error detection linear block codes have been traditionally utilized. However, there are applications where multiple errors are frequent and more complex codes are needed. Orthogonal Latin square codes are one type of codes with multiple-error-correction capability. They are of interest for memory protection because they can be decoded with low complexity and delay. This paper presents a modification to orthogonal Latin square codes that reduces the number of parity check bits to be stored in memory therefore lowering the memory overhead needed to implement the codes. The proposed codes can also be decoded with low delay and complexity. This paper also presents an evaluation of the encoder and decoder implementations for various word sizes and compares them with the standard orthogonal Latin square implementations. The results show that they are similar in terms of circuit area and introduce only a small penalty in delay.

Single Event Transient Tolerant Bloom Filter Implementations

Bloom filters have been used to reduce the delay in networking and computing applications when a set membership check is to be applied. Error sources can affect the behavior of Bloom filters resulting in a wrong outcome of this membership test and a possible effect in the systems output. Single event transients are a type of temporary errors altering the operation of combinational logic. A single event transient affecting the hash generation logic of a hardware-implemented Bloom filter can produce errors such as false negatives. This paper presents different approaches to build Bloom filters that are tolerant to single event transients occurring in the hash generation circuitry. They are compared to the use of traditional Modular Redundancy approaches. The results show that the new schemes can reduce significantly the circuit area needed to implement the Bloom filter.

A novel error correction technique for adjacent errors

Memories are one of the most widely used elements in electronic systems, and their reliability when exposed to Single Events Upsets (SEUs) has been studied extensively. As transistor sizes shrink, Multiple Bits Upsets (MBUs) are becoming an increasingly important factor in the reliability of memories exposed to radiation effects. To address this issue, Built-in Current Sensors (BICS) or Parity codes have recently been applied in conjunction with Single Error Correction/Double Error Detection (SEC-DED) codes to protect memories from MBUs. In this paper, this approach is taken one step further, proposing specific codes optimized to provide protection against errors in adjacent bits in memories. By exploiting the locality of errors within an MBU and the error detection and location capabilities of parity codes, the proposed codes result in both a better protection level and a reduced cost. This techniques improves memorys reliability by 40X compared to Hamming Codes (HC) and 2X the MTTF compared to Reed Muller Codes (RMC) for clustered MBUs

Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes

Abstract Error correction codes (ECCs) are commonly used to deal with soft errors in memory applications. Typically, Single Error Correction-Double Error Detection (SEC-DED) codes are widely used due to their simplicity. However, the phenomenon of more than one error in the memory cells has become more serious in advanced technologies. Single Error Correction-Double Adjacent Error Correction (SEC-DAEC) codes are a good choice to protect memories against double adjacent errors that are a major multiple error pattern. An important consideration is that the ECC encoder and decoder circuits can also be affected by soft errors, which will corrupt the memory data. In this paper, a method to design fault tolerant encoders for SEC-DAEC codes is proposed. It is based on the fact that soft errors in the encoder have a similar effect to soft errors in a memory word and achieved by using logic sharing blocks for every two adjacent parity bits. In the proposed scheme, one soft error in the encoder can cause at most two errors on adjacent parity bits, thus the correctness of memory data can be ensured because those errors are correctable by the SEC-DAEC code. The proposed scheme has been implemented and the results show that it requires less circuit area and power than the encoders protected by the existing methods.

Modular fault tolerant processor architecture on a SoC for space

Abstract Due to configurability feature and increasingly complex architecture, FPGAs have brought advantages to many applications such as avionics and safety critical aerospace, allowing in system reconfiguration after launch. Commercial FPGAs suffer from radiation-induced failures, which are provoked by high-energy particles in space; for this reason, fault tolerant techniques are necessary to harden these devices. This paper presents a design of a fault tolerant multicore processor architecture based on a novel modular voting strategy that fits in FPGAs and System-on-Chip (SoC) devices with an even number of processors. This architecture is implemented within a Commercial off-the-shelf (COTS) SoC that will allow to be used safely in space missions. To harden the fault tolerance of the embedded multicore processor architecture different fault tolerance techniques are combined.

Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs

Soft-processors implemented on SRAM-based FPGAs are increasingly being adopted in on-board computing for space and avionics applications due to their flexibility and ease of integration. However, efficient component-level protection techniques for these processors against radiation-induced upsets are necessary otherwise as system failures could manifest. A register file is one of the critical structures that stores vital information the processor uses related to user computations and program execution. In this paper, we present a fault tolerance technique for the register file of a microprocessor implemented in Xilinx SRAM-based FPGAs. The proposed scheme leverages the inherent implementation redundancy created by the FPGA design automation tools when mapping the register file to on-chip distributed memory. A parity-based error detection and switching logic are added for fault masking against single-bit errors. The proposed scheme has been implemented and evaluated in lowRISC, a RISC-V ISA soft-processor implementation. The effectiveness of the proposed scheme was tested using fault injection. The fault masking overhead required in terms of FPGA resources was much lower than a traditional Triple Modular Redundancy protection. Therefore, the proposed scheme is an interesting option to protect the register file of soft processors that are implemented in Xilinx FPGAs.