Costas Argyrides

Matrix Codes for Reliable and Cost Efficient Memory Chips

This paper presents a method to protect memories against multiple bit upsets and to improve manufacturing yield. The proposed method, called a Matrix code, combines Hamming and Parity codes to assure the improvement of reliability and yield of the memory chips in the presence of high defects and multiple bit-upsets. The method is evaluated using fault injection experiments. The results are compared to well-known techniques such as Reed-Muller and Hamming codes. The proposed technique performs better than the Hamming codes and achieves comparable performance with Reed-Muller codes with very favorable implementation gains such as 25% reduction in area and power consumption. It also achieves reliability increase by more than 50% in some cases. Further, the yield benefits provided by the proposed method, measured by the yield improvements per cost metric, is up to 300% better than the ones provided by Reed-Muller codes.

Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories

This paper presents a high level method called Matrix code to protect SRAM-based memories against multiple bit upsets. The proposed method combines hamming code and parity code to assure the reliability of memory in presence of multiple bit-upsets with low area and performance overhead. The method is evaluated using one million multiple-fault injection experiments; next reliability and MTTF of the protected memories are estimated based on fault injection experiments and several equations. The fault detection/correction coverage are also calculated and compared with previous methods i.e., Reed-Muller and hamming code. The results reveal that the proposed method behaves better than these methods in terms of fault detection and correction of multiple faults regarding to the area overhead.

Matrix-Based Codes for Adjacent Error Correction

Memories are one of the most widely used elements in electronic systems, and their reliability when exposed to single events upsets (SEUs) has been studied extensively. As transistor sizes shrink, multiple cells upsets (MCUs) are becoming an increasingly important factor in the reliability of memories exposed to radiation effects. To address this issue, built-in current sensors (BICS) or Parity codes have recently been applied in conjunction with single error correction/double error detection (SEC-DED) codes to protect memories from MCUs. In this paper, this approach is taken one step further, proposing specific codes optimized to provide protection against errors in adjacent bits in memories. By exploiting the locality of errors within an MCU and the error detection and location capabilities of parity codes, the proposed codes result in both a better protection level and a reduced cost. This technique improves memory reliability by 675X compared to Hamming Codes (HC) and 38X the mean time to failure (MTTF) compared to Reed Muller Codes (RMC) for clustered MCUs.

Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs

FPGAs are an appealing solution for the space-based remote sensing applications. However, in a low-earth orbit, configuration bits of SRAM-based FPGAs are susceptible to single-event upsets (SEUs). In this paper, a new protected CLB and FPGA architecture are proposed which utilize error detection and correction codes to correct SEUs occurred in LUTs of the FPGA. The fault detection and correction is achieved using online or offline fast detection and correction cycles. In the latter, detection and correction is performed in predefined error-correction intervals. In both of them error detections and corrections of k-input LUTs are performed with a latency of 2k clock cycle without any required reconfiguration and significant area overhead. The power and area analysis of the proposed techniques show that these methods are more efficient than the traditional schemes such as duplication with comparison and TMR circuit design in the FPGAs.

Single element correction in sorting algorithms with minimum delay overhead

A low delay overhead technique for the correction of errors affecting sorting algorithms, based on the use of Hamming code, is presented. Given the number of values to be sorted the expected Hamming check bits (as SUMs) are calculated, and a checker technique performs single error correction with lower delay overhead than classic approaches based on algorithm redundancy. The proposed technique has been applied to the well known bubble sorting with different sets of values to be sorted and the comparison of the resulting overhead with that imposed by the classic duplication with comparison and triple modular redundancy techniques shows that it requires lower delay overhead while providing enhanced error correction capabilities.

Improved decoding algorithm for high reliable reed muller coding

A new decoding technique for triple error Reed-Muller codes is proposed. In the best of our knowledge this is the first time that Reed-Muller Codes (RMC) as on-chip triple error correcting scheme is reported. We’ve compared the area, delay and power overhead for incorporating RMC and widely used Hamming Codes into a register file. The RMC on-chip results in 4.4X MTTF improvement with fault rate λ=10−4 and 5X reliability improvement in 512MB memory with λ=10−5 upsets/bit per day sacrificing area power and delay.

Multiple Upsets Tolerance in SRAM Memory

This paper presents a high level method called matrix code to protect SRAM-based memories against multiple bit upsets. The proposed method combines hamming code and parity code to assure the reliability of memory in presence of multiple bit-upsets with low area and performance overhead. The method is evaluated using one million multiple-fault injection experiments; next reliability and MTTF of the protected memories are estimated based on fault injection experiments and several equations. The fault detection/correction coverage are also calculated and compared with previous methods i.e., Reed-Muller and hamming code. The results reveal that the proposed method behaves better than these methods in terms of fault detection and correction of multiple faults regarding to the area overhead.

Reliability Analysis of H-Tree Random Access Memories Implemented With Built in Current Sensors and Parity Codes for Multiple Bit Upset Correction

This paper presents an efficient technique for designing high defect tolerance Static Random Access Memories (SRAMs) with significantly low power consumption. The new approach requires drastically lower area overhead, simpler encoding and decoding algorithms, and zero fault-detection latency time for multiple error detection when compared to conventional techniques. The approach is based on the use of Built-In-Current-Sensors (BICS) to detect the abnormal current dissipation in the memory power-bus to improve the reliability of H-Tree SRAM memories. This abnormal current is the result of a single-event upset (SEU) in the memory, and it is generated during the inversion of the state of the memory cell being upset (bit-flip). We demonstrate the assertions of the proposed approach with HSPICE simulations, and a reliability analysis that combines BICS with single-parity bit (or Hamming codes) per SRAM word to perform error correction. Furthermore, the basic infrastructure provided by this approach can also be used to dynamically reconfigure the SRAM memory to save power, and to leverage fabrication yield.

Efficient error detection in Double Error Correction BCH codes for memory applications

Abstract To prevent soft errors from causing data corruption, memories are commonly protected with Error Correction Codes (ECCs). To minimize the impact of the ECC on memory complexity simple codes are commonly used. For example, Single Error Correction (SEC) codes, like Hamming codes are widely used. Power consumption can be reduced by first checking if the word has errors and then perform the rest of the decoding only when there are errors. This greatly reduces the average power consumption as most words will have no errors. In this paper an efficient error detection scheme for Double Error Correction (DEC) Bose–Chaudhuri–Hocquenghem (BCH) codes is presented. The scheme reduces the dynamic power consumption so that it is the same that for error detection in a SEC Hamming code.

Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement

In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of the memory cell being upset. The current checking is performed on an H-tree SRAM in different ways. We demonstrate the assertions of the proposed technique by performing a reliability analysis while combining current monitoring with a single-parity bit or Hamming codes per RAM word to perform single or multiple error correction.