Juan José Raygoza Panduro

Copper and Core Loss Minimization for Induction Motors Using High-Order Sliding-Mode Control

A novel nonlinear affine model for an induction motor with core loss is developed in the well-known (α, β) stationary reference frame, where the core is represented with a resistance in parallel with a magnetization inductance. Then, an optimal rotor flux modulus is calculated such that the power loss due to stator, rotor, and core resistances is minimized, and as a consequence, the motor efficiency is raised; therefore, this flux modulus is forced to be tracked by the induction motor along with a desired rotor velocity by means of a high-order sliding-mode controller, the supertwisting algorithm. Using a novel Lyapunov function, the closed-loop stability of the system is demonstrated. Moreover, a classical sliding-mode observer is designed for the estimation of unmeasurable variables like rotor fluxes and magnetization currents. For the load torque, a Luenberger observer is designed. The performance of the proposed controller is finally studied by simulation and experimental tests. It was observed that the steady-state optimal flux signal corresponds to the load torque profile. This fact suggests that the flux demand is the necessary one to produce the electric torque that can cancel out the load torque.

Design and implementation of a DC motor control using Field Programmable Analog Arrays

This work presents an implementation of a control algorithm for DC motors using a technology that is gaining popularity, known as Field Programmable Analog Array (FPAA). The mathematical model of the DC motor and control are scaled to adjust the permitted voltages for the FPAA. Simulations of the implementation of the control algorithm with analog circuits are carried out where the good performance of the closed loop system is verified. Real Time experimentation results also validate the proposed design and implementation of the control Algorithm.

Space-time AER protocol receiver asynchronously controlled on FPGA

Neuromorphic systems have been increasing in size and complexity in recent years, due to the adoption of the Address-Event Representation (AER) as a standard for transmitting signals among chips, and building multi-chip event-based systems. The data amount and speed are keys in address-event receiver devices. Actual receiver designs are based on VLSI and ASIC-FPGA implementation. In this article we present a receiver implemented on reconfigurable devices FPGA, preserving the virtues of useful reconfiguration for design and development inherent of FPGAs. We present the design of the receiver and experimental results, which show the data management capability and speed of reception.

Architecture design to optimize multipliers in FPGAs based on Maya multiplying method

The Mayan binary multiplier is an architecture to simplify and optimize the multiplication implemented in FPGAs. This architecture is based on the Maya multiplication method or Tzeltal. The architecture takes advantage of the parallelism of FPGAs grouping multipliers for generating the partial products. The multiplication is accelerated by decreasing the number of sums to be performed. This new approach provides properties that improve arithmetic calculations.

A Hardware Implementation of a Unit for Geometric Algebra Operations With Parallel Memory Arrays (Abstract Only)

Geometric algebra (GA) is a powerful and versatile mathematical tool which helps to intuitively express and manipulate complex geometric relationships. It has recently been used in engineering problems such computer graphics, machine vision, robotics, among others. The problem with GA in its numeric version is that it requires many arithmetic operations, and the length of the input vectors is unknown until runtime in a generic architecture operating over homogeneous elements. Few works in hardware architectures for GA were developed to improve the performance in GA applications. In this work, a hardware architecture of a unit for GA operations (geometric product) for FPGA is presented. The main contribution of this work is the use of parallel memory arrays with access conflict avoidance for dealing with the issue of unknown length of input/output vectors, the intention is to reduce memory wasted when storing the input and output vectors. In this first stage of the project, we have implemented only a single access function (fixed-length) in the memory array in order to test the core of geometric product. In future works we will implement a full set of access functions with different lengths and shapes. In this work, only the simulations are presented; in the future, we will also present the experimental resultsGeometric algebra (GA) is a powerful and versatile mathematical tool which helps to intuitively express and manipulate complex geometric relationships. It has recently been used in engineering problems such computer graphics, machine vision, robotics, among others. The problem with GA in its numeric version is that it requires many arithmetic operations, and the length of the input vectors is unknown until runtime in a generic architecture operating over homogeneous elements. Few works in hardware architectures for GA were developed to improve the performance in GA applications. In this work, a hardware architecture of a unit for GA operations (geometric product) for FPGA is presented. The main contribution of this work is the use of parallel memory arrays with access conflict avoidance for dealing with the issue of unknown length of input/output vectors, the intention is to reduce memory wasted when storing the input and output vectors. In this first stage of the project, we have implemented only a single access function (fixed-length) in the memory array in order to test the core of geometric product. In future works we will implement a full set of access functions with different lengths and shapes. In this work, only the simulations are presented; in the future, we will also present the experimental results

Characterization technique to implement self-timed cells for VLSI design blocks

In this article, a methodology to obtain the characterization of the standard cell library called SXLIB is presented, this library is available within Alliance tools. The later proposal is developed based on the spreading analysis that the signal has throughout each cell, this with the objective of obtaining a delay time according to the technology of the manufactures receiver. This characterization technique can be used with any set of standard cells, for a manufacturing technology that differs by the default one used by Alliance, then, the results of the new characterization are presented of the specified library SXLIB. The importance of knowing the spreading time of the signal, is due to the required time to include the necessary delays in the design of self-timed structures. This is, one of the key phases of the design and synthesis process, expressed in structural language VHDL that generates Alliance tools. Throughout this phase, the designer will prove that the IC works under the desired behavior, in form (logic operation) as in time (maximum and minimum delays, maximum work frequencies, etc.). That is because the obtained results from using the characterized library represent a key point in the design of self-timed structures.

Methodology for the implementation of a SIMULATOR of electric transients on FPGA

This article describes the implementation of a real time electric circuit simulator prototype on a reconfigurable device. Real time measurement are presented and validated through specialized software. The proposed architecture relies on particular hardware techniques, such as parallel design, looking to satisfy the requirements of computation time.