Susana Ortega-Cisneros

Copper and Core Loss Minimization for Induction Motors Using High-Order Sliding-Mode Control

A novel nonlinear affine model for an induction motor with core loss is developed in the well-known (α, β) stationary reference frame, where the core is represented with a resistance in parallel with a magnetization inductance. Then, an optimal rotor flux modulus is calculated such that the power loss due to stator, rotor, and core resistances is minimized, and as a consequence, the motor efficiency is raised; therefore, this flux modulus is forced to be tracked by the induction motor along with a desired rotor velocity by means of a high-order sliding-mode controller, the supertwisting algorithm. Using a novel Lyapunov function, the closed-loop stability of the system is demonstrated. Moreover, a classical sliding-mode observer is designed for the estimation of unmeasurable variables like rotor fluxes and magnetization currents. For the load torque, a Luenberger observer is designed. The performance of the proposed controller is finally studied by simulation and experimental tests. It was observed that the steady-state optimal flux signal corresponds to the load torque profile. This fact suggests that the flux demand is the necessary one to produce the electric torque that can cancel out the load torque.

Implementation of a Wireless Control System with Self Timed Activation for Mobile Robots

This work presents the implementation of a wireless system for the control of mobile robots using circuits with Self-Timed (ST) Synchronization, implemented in reconfigurable devices FPGAs. The system is composed of a global network of small ST processors, which will develop independent processes communicated by means of modules of wireless transmission that form the network of activation of peripheral units. The proposal of this project consists of developing a wireless network of processors with fixed stations and mobiles, designed to low power by means of the use of circuits with Self-Timed synchronization. Every station of transmission consists in a ST microprocessor and a Xbee transmitter that transmits in a wireless way the instructions to the robot.

FPGA implementation of a synchronous and self-timed neuroprocessor

This article presents the implementation of a neuroprocessor based on a self-organizing map (SOM) architecture. The processor presents a hybrid structure both synchronous and self-timed. Where the neuronal network blocks (SOM) are synchronized with a protocol of 4 phases, for the control of data flow. The neuroprocessor was designed for the analysis and classification of tension deformation patterns of the knee ligaments. The circuit is programmable and recognizes different sequences of movement patterns for a knee joint with damage to the anterior cruciate ligament (ACL). This design is part of an electronic system for the rehabilitation of injuries to the ACL and the dynamic study of the knee. The circuit is implemented in an FPGA Virtex II.

Discrete-time sensorless control of permanent magnet synchronous motors

In this work, a sensorless control scheme was designed for permanent magnet synchronous motors based on a sampled model. The discrete-time model was obtained using the Symplectic Euler method. Taking such model along with voltage and current measurements, an observer is designed for rotor position and velocity estimation. Then, the rotor velocity is forced to track a desired reference signal by means of a discrete-time quasi-sliding mode technique.

Design of a Mathematical Unit in FPGA for the Implementation of the Control of a Magnetic Levitation System

This paper presents the design and implementation of an automatically generated mathematical unit, from a program developed in Java that describes the VHDL circuit, ready to be synthesized with the Xilinx ISE tool. The core contains diverse complex operations such as mathematical functions including sine and cosine, among others. The proposed unit is used to synthesize a sliding mode controller for a magnetic levitation system. This kind of systems is used in industrial applications requiring high level of mathematical calculations in small time periods. The core is designed to calculate trigonometric and arithmetic operations in such a way that each function is performed in a clock cycle. In this paper, the results of the mathematical core are shown in terms of implementation, utilization, and application to control a magnetic levitation system.

Implementation of SoC Based Real-Time Electromagnetic Transient Simulator

Real-time electromagnetic transient simulators are important tools in the design stage of new control and protection systems for power systems. Real-time simulators are used to test and stress new devices under similar conditions that the device will deal with in a real network with the purpose of finding errors and bugs in the design. The computation of an electromagnetic transient is complex and computationally demanding, due to features such as the speed of the phenomenon, the size of the network, and the presence of time variant and nonlinear elements in the network. In this work, the development of a SoC based real-time and also offline electromagnetic transient simulator is presented. In the design, the required performance is met from two sides, (a) using a technique to split the power system into smaller subsystems, which allows parallelizing the algorithm, and (b) with specialized and parallel hardware designed to boost the solution flow. The results of this work have shown that for the proposed case studies, based on a balanced distribution of the node of subsystems, the proposed approach has decreased the total simulation time by up to 99 times compared with the classical approach running on a single high performance 32-bit embedded processor ARM-Cortex A9.

Design of a Mathematical Unit in FPGAs for the Implementation of the Control of a System of Magnetic Levitation

This paper presents the design and implementation of a mathematical unit, which is generated automatically, from a program elaborated in Java that describes the circuit in VHDL, ready to be synthesized with the Xilinx ISE tool. The core contains diverse complex operations such as: mathematical functions including; sine, cosine, among others. The proposed unit is used to synthesize a sliding mode controller for a magnetic levitation system. This kind of system is used in industrial applications requiring high level mathematical calculations in small time periods. The core is designed to calculate trigonometric and arithmetic operations in such a way that each function is performed in a clock cycle. In this paper the results of the mathematical core are shown in terms of implementation, utilization and application to control a magnetic levitation system.

American Sign Language Alphabet Recognition Using a Neuromorphic Sensor and an Artificial Neural Network

This paper reports the design and analysis of an American Sign Language (ASL) alphabet translation system implemented in hardware using a Field-Programmable Gate Array. The system process consists of three stages, the first being the communication with the neuromorphic camera (also called Dynamic Vision Sensor, DVS) sensor using the Universal Serial Bus protocol. The feature extraction of the events generated by the DVS is the second part of the process, consisting of a presentation of the digital image processing algorithms developed in software, which aim to reduce redundant information and prepare the data for the third stage. The last stage of the system process is the classification of the ASL alphabet, achieved with a single artificial neural network implemented in digital hardware for higher speed. The overall result is the development of a classification system using the ASL signs contour, fully implemented in a reconfigurable device. The experimental results consist of a comparative analysis of the recognition rate among the alphabet signs using the neuromorphic camera in order to prove the proper operation of the digital image processing algorithms. In the experiments performed with 720 samples of 24 signs, a recognition accuracy of 79.58% was obtained.

FPGA Implementation of a NARX Network for Modeling Nonlinear Systems

This paper presents the FPGA implementation of a NARX neural network for the modeling nonlinear systems. The complete neural architecture was implemented with Verilog language in Xilinx ISE Tool with the Virtex-6 FPGA ML605 Evaluation Kit. All operations, such as data processing, weight connections, multipliers, adders and activation function were performed using floating point format, because allows high precision in operations with high complexity. Some resources of Xilinx were used such as multipliers and CORE blocks, and the hyperbolic tangent of the activation is realized based on Taylor series. To validate the implementation results, the NARX network was used to model the inverse characteristics of a power amplifier. The results obtained in the simulation and the FPGA implementation shown a high correspondence.

Real time hardware accelerator for image filtering

The image processing nowadays is a field in development, many image filtering algorithms are tested every day; however, the main hurdles to overcome are the difficulty of implementation or the time response in a general purpose processors. When the amount of data is too big, a specific hardware accelerator is required because a software implementation or a generic processor is not fast enough to respond in real time. In this paper optimal hardware implementation is proposed for extracting edges and noise reduction of an image in real time. Furthermore, the hardware configuration is flexible with the ability to select between power and area optimization or speed and performance. The results of algorithms implementation are reported.