Juan José Serrano
Polytechnic University of Valencia
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Publication
Featured researches published by Juan José Serrano.
real time technology and applications symposium | 1996
José V. Busquets-Mataix; Juan José Serrano; Rafael Ors; Pedro J. Gil; Andy J. Wellings
Cache memories are commonly avoided in real time systems because of their unpredictable behavior. Recently, some research has been done to obtain tighter bounds on the worst case execution time (WCET) of cached programs. These techniques usually assume a non preemptive underlying system. However, some techniques can be applied to allow the use of caches in preemptive systems. The paper describes how to incorporate the effect of instruction cache to the Response Time schedulability Analysis (RTA). RTA is an efficient analysis for preemptive fixed priority schedulers. We also compare through simulations the results of such an approach to both cache partitioning (increase of the cache predictability by assigning private cache partitions to tasks) and CRMA (Cached RMA: cache effect is incorporated in the utilization based rate monotonic schedulability analysis). The results show that the cached version of RTA (CRTA) clearly outperforms CRMA, however the partitioning scheme may be better depending on the system configuration. The obtained results bound the applicability domain for each method for a variety of hardware and workload configurations. The results can be used as design guidelines.
Sensors | 2014
Salvador Climent; Antonio J. Sánchez; Juan Vicente Capella; Juan José Serrano
This survey aims to provide a comprehensive overview of the current research on underwater wireless sensor networks, focusing on the lower layers of the communication stack, and envisions future trends and challenges. It analyzes the current state-of-the-art on the physical, medium access control and routing layers. It summarizes their security threads and surveys the currently proposed studies. Current envisioned niches for further advances in underwater networks research range from efficient, low-power algorithms and modulations to intelligent, energy-aware routing and medium access control protocols.
Sensors | 2012
Salvador Climent; Juan Vincente Capella; Juan José Serrano
The specific characteristics of underwater environments introduce new challenges for networking protocols. In this paper, a specialized architecture for underwater sensor networks (UWSNs) is proposed and evaluated. Experiments are conducted in order to analyze the suitability of this protocol for the subaquatic transmission medium. Moreover, different scheduling techniques are applied to the architecture in order to study their performance. In addition, given the harsh conditions of the underwater medium, different retransmission methods are combined with the scheduling techniques. Finally, simulation results illustrate the performance achievements of the proposed protocol in end-to-end delay, packet delivery ratio and energy consumption, showing that this protocol can be very suitable for the underwater medium.
Sensors | 2012
Antonio J. Sánchez; Sara Blanc; Pedro Yuste; Angel Perles; Juan José Serrano
This paper is focused on the description of the physical layer of a new acoustic modem called ITACA. The modem architecture includes as a major novelty an ultra-low power asynchronous wake-up system implementation for underwater acoustic transmission that is based on a low-cost off-the-shelf RFID peripheral integrated circuit. This feature enables a reduced power dissipation of 10 μW in stand-by mode and registers very low power values during reception and transmission. The modem also incorporates clear channel assessment (CCA) to support CSMA-based medium access control (MAC) layer protocols. The design is part of a compact platform for a long-life short/medium range underwater wireless sensor network.
dependable systems and networks | 2003
Pedro Yuste; David de Andrés; Lenin Lemus; Juan José Serrano; Pedro J. Gil
Software implemented fault injection techniques (SWIFI) enable emulation of hardware and software faults. This emulation can be based on debugging mechanisms of general purpose processors [1] or in special debugging ports of embedded processors [2]. A well-known drawback of existing SWIFI tools rely on the temporal overhead introduced in the target system. This overhead is a problem when validating real-time systems. This paper presents a new SWIFI tool (INERTE) that solves this problem by using a standard debug interface called Nexus [3]. Using Nexus, system memory can be accessed at runtime without any intrusion in the target system. Thus, INERTE is able to inject transient faults without any temporal overhead.
embedded and real-time computing systems and applications | 1996
José V. Busquets-Mataix; Juan José Serrano; Rafael Ors; Pedro J. Gil; Andy J. Wellings
Cache memories have been traditionally precluded in real-time systems because of their unpredictable behavior. The needs of better performance have motivated the development of tools to obtain tighter bounds on the worst-case execution time (WCET) of cached programs. However, they do not allow preemption, because from the point of view of program analysis, the number of preemptions is unknown. To face this problem, the cache-related preemption cost can be considered in the schedulability analysis, or annulled by the use of private cache partitions. Regarding the first approach, in a previous paper we described how to incorporate the effect of the cache to the Response Time schedulability Analysis (RTA). RTA is an efficient analysis for preemptive fixed-priority schedulers. In this paper, we have improved such a technique by taking into account the harmonic relations amongst task frequencies. The resulting analysis is applied to sample task-sets to illustrate the potential gains in terms of schedulable utilization, particularly for highly demanding task-sets.
Sensors | 2011
Juan Vicente Capella; Angel Perles; Alberto Bonastre; Juan José Serrano
We present a set of novel low power wireless sensor nodes designed for monitoring wooden masterpieces and historical buildings, in order to perform an early detection of pests. Although our previous star-based system configuration has been in operation for more than 13 years, it does not scale well for sensorization of large buildings or when deploying hundreds of nodes. In this paper we demonstrate the feasibility of a cluster-based dynamic-tree hierarchical Wireless Sensor Network (WSN) architecture where realistic assumptions of radio frequency data transmission are applied to cluster construction, and a mix of heterogeneous nodes are used to minimize economic cost of the whole system and maximize power saving of the leaf nodes. Simulation results show that the specialization of a fraction of the nodes by providing better antennas and some energy harvesting techniques can dramatically extend the life of the entire WSN and reduce the cost of the whole system. A demonstration of the proposed architecture with a new routing protocol and applied to termite pest detection has been implemented on a set of new nodes and should last for about 10 years, but it provides better scalability, reliability and deployment properties.
mobile adhoc and sensor systems | 2011
Antonio J. Sánchez; Sara Blanc; Pedro Yuste; Juan José Serrano
This paper presents a new Acoustic-Triggered Wake-Up system specially useful to Underwater Wireless Sensor Networks built with low-power consumption architectures. The work includes both the wake-up system description and a comparison with previous works carried out under similar features. These comparisons demonstrate the energy benefits of this new system which requires no additional hardware within the transmission and a single but efficient AT-WUp module in the reception.
Microprocessors and Microsystems | 1999
José Carlos Campelo; Francisco Rodríguez; Alicia Rubio; Rafael Ors; Pedro J. Gil; Lenin Lemus; Jose Vicente Busquets; José Albaladejo; Juan José Serrano
Abstract Nowadays, distributed architectures are the base of many manufacturing systems. Some aspects like fault-tolerance, system validation and design process are very important in the development of these systems. In this paper we study the dependability of three different architectures of a distributed system, and we show the development of both physical and logical fault injectors and the implementation of local performance monitors. We also study the impact of checkpointing mechanisms on the system performance in a control system based on a CAN network. Finally we propose a distributed system design methodology based on codesign.
VLSI Circuits and Systems V | 2011
Antonio J. Sánchez; J. Aguilar; Sara Blanc; Juan José Serrano
A critical issue of Wireless Sensor Networks circuits is energy management. This work presents a Radio-Triggered Wake-Up solution designed and developed for WSN based systems. The proposed circuit manages, in a simple and efficient way, node switching between sleep mode and both receiving or transmitting active modes. It uses a HW hearing circuit, which lowers power consumption and avoids extra processing on the main microcontroller. The weak-up is selective with predefined recognition patterns without the microcontroller intervention. Furthermore, it is tiny in size, and the whole circuit is suitable for single CMOS chip integration. The circuit has been tested to demonstrate the Wake- Up proposal worthiness. With only 8.7 microwatts of power consumption (@ 3.0 Vdc) the system successfully Wake-Up nodes up to 15 meters away from the transmission source. This performance improves solutions presented in previous research works.