Pedro J. Gil

Adding instruction cache effect to schedulability analysis of preemptive real-time systems

Cache memories are commonly avoided in real time systems because of their unpredictable behavior. Recently, some research has been done to obtain tighter bounds on the worst case execution time (WCET) of cached programs. These techniques usually assume a non preemptive underlying system. However, some techniques can be applied to allow the use of caches in preemptive systems. The paper describes how to incorporate the effect of instruction cache to the Response Time schedulability Analysis (RTA). RTA is an efficient analysis for preemptive fixed priority schedulers. We also compare through simulations the results of such an approach to both cache partitioning (increase of the cache predictability by assigning private cache partitions to tasks) and CRMA (Cached RMA: cache effect is incorporated in the utilization based rate monotonic schedulability analysis). The results show that the cached version of RTA (CRTA) clearly outperforms CRMA, however the partitioning scheme may be better depending on the system configuration. The obtained results bound the applicability domain for each method for a variety of hardware and workload configurations. The results can be used as design guidelines.

Comparison and application of different VHDL-based fault injection techniques

Compares different VHDL-based fault injection techniques: simulator commands, saboteurs and mutants for the validation of fault tolerant systems. Some extensions and implementation designs of these techniques have been introduced. Also, a wide set of non-usual fault models have been implemented. As an application, a fault tolerant microcomputer system has been validated. Faults have been injected using an injection tool developed by the GSTF. We have injected both transient and permanent faults on the system model, using two different workloads. We have studied the pathology of the propagated errors, measured their latencies, and calculated both detection and recovery coverages. Preliminary results show that coverages for transient faults can be obtained quite accurately with any of the three techniques. This enables the use of different abstraction level models for the same system. We have also verified significant differences in implementation and simulation cost between the studied injection techniques.

A prototype of a VHDL-based fault injection tool: description and application

This paper presents the prototype of an automatic and model-independent fault injection tool, to be used on an IBM-PC (or compatible) platform. The tool has been built around a commercial VHDL simulator and it is thought to implement different fault injection techniques. With this tool, a wide range of transient and permanent faults can be injected into medium-complexity models. Another remarkable aspect of the tool is the fact that it can analyse the results obtained from injection campaigns, in order to study the Error Syndrome of the system model and/or validate its fault-tolerance mechanisms. Some results of various fault injection campaigns carried out to validate the Dependability of a fault-tolerant microcomputer system are shown. We have analysed the pathology of the propagated errors, measured their latencies, and calculated both error detection and recovery latencies and coverages.

Improvement of fault injection techniques based on VHDL code modification

Fault injection techniques based on the use of VHDL as design language offer important advantages with regard to other fault injection techniques. First, as they can be applied during the design phase of the system, they allow reducing the time-to-market. Second, this type of techniques presents high controllability and reachability. Among the different techniques, those based on the use of saboteurs and mutants are especially attractive due to their high capability of fault modeling. However, it is difficult to implement automatically these techniques in a fault injection tool, mainly the insertion of saboteurs and the generation of mutants. In this paper, we present new models of saboteurs and mutants that can be easily applicable in VFIT, a fault injection tool developed by the Fault-Tolerant Systems Research Group (GSTF) of the Technical University of Valencia.

Fault Injection into VHDL Models: Experimental Validation of a Fault Tolerant Microcomputer System

This work presents a campaign of fault injection to validate the dependability of a fault tolerant microcomputer system. The system is duplex with cold stand-by sparing, parity detection and a watchdog timer. The faults have been injected on a chip-level VHDL model, using an injection tool designed with this purpose. We have carried out a set of injection experiments (with 3000 injections each), injecting transient and permanent faults of types stuck-at, open-line and indetermination on both the signals and variables of the system, running a workload. We have analysed the pathology of the propagated errors, measured their latency, and calculated both detection and recovery coverage. We have also studied the influence with the fault duration and fault distribution. For instance, system detection coverage (including noneffective faults) is 98% and the system recovery coverage is 95% for short transient faults (0.1 clock cycles).

A study of the effects of transient fault injection into the VHDL model of a fault-tolerant microcomputer system

This work presents a campaign of fault injection to validate the dependability of a fault tolerant microcomputer system. The system is duplex with cold stand-by sparing, parity detection and a watchdog timer. The faults have been injected on a chip-level VHDL model, using an injection tool designed for this purpose. We have carried out a set of injection experiments (with 3000 injections each), injecting transient faults of types stuck-at, bit-flip, indetermination and delay on both the signals and variables of the system, running two different workloads. We have analysed the pathology of the propagated errors, measured their latency, and calculated both detection and recovery coverage. For instance, system detection coverages (including non-effective errors) up to 98%, and system recovery coverage up to 94% have been obtained for short transient faults.

Non-intrusive Software-Implemented Fault Injection in Embedded Systems

Critical embedded systems, like those used in avionics or automotive, have strong dependability requirements and most of them must face with fault tolerance. One of the methods typically used to validate fault tolerance mechanisms is fault injection. The idea is to study the behavior of the system in presence of faults in order to determine whether the system behaves properly or not. Software-implemented fault injection (SWIFI) techniques enable fault injection to be performed by software. Although interesting, major drawbacks of existing SWIFI techniques are the temporal and the spatial overheads they induced in the systems under study. The reduction of these overheads is thus crucial, in order to be confident on the results and conclusions of a SWIFI experiment. This paper focuses on this problem. It proposes a new non-intrusive SWIFI technique for injecting faults in embedded (system-on-chip) applications. The technique exploits the features of a standard debugging interface for embedded systems, called Nexus, in order to inject faults without temporal overhead. Then, Nexus features are also exploited in order to observe, without spatial intrusion, the behavior of the target system in presence of the injected faults. In other words, the embedded system under study can be controlled (for injecting faults) and observed (for tracing its behavior) without customizing its original structure or altering its normal execution. Since based on Nexus, the technique has also the benefit of being applicable to any Nexus-compliant system. In order to illustrate the potentials of the approach, we use an automotive embedded control unit application as a case study. Some preliminary results obtained from the experiments performed are also discussed.

Study, comparison and application of different VHDL-based fault injection techniques for the experimental validation of a fault-tolerant system

In this work different VHDL-based fault injection techniques (simulator commands, saboteurs and mutants) have been compared and applied in the validation of a fault-tolerant system. Some extensions and implementation designs of these techniques have been introduced. As a complement of these injection techniques, a wide set of fault models (including several non-usual models) have been implemented. We have injected both transient and permanent faults on the system model, using two different workloads, with the help of a fault injection tool that we have developed. We have studied the pathology of the propagated errors, measured their latencies, and calculated both detection and recovery coverages. Results show that coverages for transient faults can be obtained quite accurately with any of the three techniques. This enables the use of different abstraction level models for the same system. We have also verified significant differences in implementation and simulation cost between the studied injection techniques. q 2002 Elsevier Science Ltd. All rights reserved.

INERTE: integrated nexus-based real-time fault injection tool for embedded systems

Software implemented fault injection techniques (SWIFI) enable emulation of hardware and software faults. This emulation can be based on debugging mechanisms of general purpose processors [1] or in special debugging ports of embedded processors [2]. A well-known drawback of existing SWIFI tools rely on the temporal overhead introduced in the target system. This overhead is a problem when validating real-time systems. This paper presents a new SWIFI tool (INERTE) that solves this problem by using a standard debug interface called Nexus [3]. Using Nexus, system memory can be accessed at runtime without any intrusion in the target system. Thus, INERTE is able to inject transient faults without any temporal overhead.

Towards benchmarking routing protocols in wireless mesh networks

Wireless mesh networks (WMNs) establish a new, quick and low-cost alternative to provide communications when deploying a fixed infrastructure that could result prohibitive in terms of either time or money. During last years, the specification of multi-hop routing protocols for WMNs has been promoted, leading to their recent exploitation in commercial solutions. The selection of routing protocols for integration in WMNs requires the evaluation, comparison and ranking of eligible candidates according to a representative set of meaningful measures. In this context, the development of suitable experimental techniques to balance different features of each protocol is an essential requirement. This paper copes with this challenging task by proposing a benchmarking methodology to experimentally evaluate and compare the behaviour of these protocols. The feasibility of the proposed approach is illustrated through a simple but real (non-simulated) case study and reflects to what extent this methodology can be useful in increasing our knowledge on how real WMNs behave in practice.