Juan M. Meneses

VLSI architecture for motion estimation using the block-matching algorithm

In this paper an architecture is described that implements motion estimation in image coding, using a block-matching algorithm and an exhaustive search method. The architecture, EST256, consists of 256 processor elements, deals with a search area of -8/+7 and performs 11 GOPS (subtraction, absolute value determination, accumulation and comparison). It is implemented with ES2 0.7 /spl mu/m double-metal-layer CMOS technology. This ASIC is cascadable to deal with bigger search areas.

Some Notes on Power Management on FPGA-Based Systems

Although the energy required to perform a logic operation has continuously dropped at least by ten orders of magnitude since early vacuum-tube electronics [1], the increasing clock frequency and gate density of the current integrated circuits has appended power consumption to traditional design trade-offs. This paper explore the usefullness of some low-power design methods based on architectural and implementation modifications, for FPGA-based electronic systems. The contribution of spurious transitions to the overal consumption is evidenced and main strategies for its reduction are analized. The efectiveness of pipelining and partitioning inprovements as low-power design methodologies are quantified by case-studies based on array multipliers. Moreover, a methodology suitable for FPGAs power analysis is presented.

Some experiments about wave pipelining on FPGA's

Wave pipelining offers a unique combination of high speed, low latency, and moderate power consumption. The construction of wave pipelines is benefited by the use of gates and buffers with data-independent delays and the knowledge of the interconnection delays. These two features are present in several SRAM-based field programmable gate arrays (FPGAs): look-up tables (LUTs) allow the designer to mask the delay of different gates and combinational functions, and the timing characteristics of each wire segment are a priori known. This work describes a set of experiments about wave pipelining on FPGAs. The results show that a 13-LUT logic depth circuit mapped on an XC4005PC84-6 runs as high as 85 MHz (single phase clocking) or 80 MHz (intentionally skewed clocking), exhibiting a latency of 95 ns. This high throughput/latency ratio is unattainable using classic pipelining.

Efficient Forest Fire Detection Index for Application in Unmanned Aerial Systems (UASs)

This article proposes a novel method for detecting forest fires, through the use of a new color index, called the Forest Fire Detection Index (FFDI), developed by the authors. The index is based on methods for vegetation classification and has been adapted to detect the tonalities of flames and smoke; the latter could be included adaptively into the Regions of Interest (RoIs) with the help of a variable factor. Multiple tests have been performed upon database imagery and present promising results: a detection precision of 96.82% has been achieved for image sizes of 960 × 540 pixels at a processing time of 0.0447 seconds. This achievement would lead to a performance of 22 f/s, for smaller images, while up to 54 f/s could be reached by maintaining a similar detection precision. Additional tests have been performed on fires in their early stages, achieving a precision rate of p = 96.62%. The method could be used in real-time in Unmanned Aerial Systems (UASs), with the aim of monitoring a wider area than through fixed surveillance systems. Thus, it would result in more cost-effective outcomes than conventional systems implemented in helicopters or satellites. UASs could also reach inaccessible locations without jeopardizing people’s safety. On-going work includes implementation into a commercially available drone.

Wave pipelines via look-up tables

Look-up tables (LUTs) allow the delay of digital blocks with different types of gates or different logic depth to be equalized; thus, they could be a useful building block for the construction of wave pipelined circuits. In this paper, this alternative is explored by using a RAM-based FPGA. An experimental LUT-based wave pipeline 7-bit array multiplier has been constructed. The main results, for an intentionally skewed clock synchronization strategy, show that it is possible to obtain throughputs as high as 80 MHz with 8 waves running in a 13-LUT logic depth combinational circuit. The prototype presents a continuous range of frequency operation and exhibits an acceptable dependence with power supply variations. In terms of fast-prototyping, wave pipelining on FPGAs allows the designers to obtain a unique combination of high-throughput and minimum-latency.

A High-Performance Architecture with a Macroblock-Level-Pipeline for MPEG-2 Coding

A high-performance parallel and pipelined architecture (MViP) has been proposed for MPEG-2 coding. A macrocell for use in an ASIC has been designed and implemented using ES2 0.7 ?m dual-layer-metal CMOS technology. This macrocell consists of about 120,000 equivalent gates and is able to execute, in real time, the Loop of an MPEG-2 coder for main profile/main level (MP@ML) resolution when running at 40 MHz. MViP is made up of several specific-purpose units (SPUs), an RISC core processor, banks of internal memory and an optimized crossbar network which lets these pipelined SPUs and RISC core work in parallel at a macroblock-level-pipeline, greatly increasing silicon efficiency.

A flexible architecture for H.263 video coding

In this paper a very flexible and efficient architecture that implements the core of a video coder according to Rec. H.263 is presented. It consists of a RISC processor that controls the scheduling of a set of specialized processors for the transforms (DCT and IDCT), quantizers (DQ and IQ), motion estimation and motion compensation (ME/MC). The architecture also includes preprocessing modules for the input video signal from the camera and interfaces for the external video memory and the H.263 bit-stream generation. The architecture has been written in synthesizable Verilog and tested using standard video sequences. It has also been prototyped into a development system based on an FPGA and a RISC.

FPGA Implementation of the Block-Matching Algorithm for Motion Estimation in Image Coding

In this paper we describe an FPGA implementation of a previously proposed architecture that performs motion estimation in image coding using the full-search Block-Matching algorithm. The emphasis of this work is to evaluate the suitability of this technology to solve the motion estimation problem (one of the most demanding parts of the image coding process). The result is a two-FPGA implementation that performs at 925 MOPS.

A modular middleware approach for exergaming

This paper presents the design of a new exergaming environment consisting of a modular middleware tool aimed at serving for intelligent adventure games. The middleware provides a modular and user-adaptive interface for data exchange between different devices (to date it supports a motion capture camera, a mobile phone, and a VR headset) and Blender. The target group is formed by young people between ages 6 to 26 with different physical diseases (muscular dystrophy, cerebral palsy, accidents, etc.). The gaming environment focuses especially on user awareness, immersion, and adaptability to special needs.

Usage of VR Headsets for Rehabilitation Exergames

The work presented here is part of a large project aimed at finding new ways to tackle exergames used for physical rehabilitation. The preferred user group consists of physically impaired who normally cannot use commercially available games; our approach wants to fill a niche and allow them to get the same playing experience like healthy. Four exercises were implemented with the Blender Game engine and connected to a motion capture device (Kinect) via a modular middleware. The games incorporate special features that enhance weak user movements, such that the avatar reacts in the same way as for persons without physical restrictions. Additionally, virtual reality glasses have been integrated to achieve a more immersive feeling during play. In this work, we compare the results of preliminary user tests, performed with and without VR glasses. Test outcomes are good for motion amplification in some of the games but do not present generally better results when using the VR glasses.