Eduardo I. Boemo

Design of high-speed multiplierless filters using a nonrecursive signed common subexpression algorithm

In this work, a new algorithm called nonrecursive signed common subexpression elimination (NR-SCSE) is discussed, and several applications in the area of multiplierless finite-impulse response (FIR) filters are developed. While the recursive utilization of a common subexpression generates a high logic depth into the digital structure, the NR-SCSE algorithm allows the designer to overcome this problem by using each subexpression once. The paper presents a complete description of the algorithm, and a comparison with two other well-known options: the graph synthesis, and the classical common subexpression elimination technique. Main results show that the NR-SCSE implementations of several benchmark circuits offer the best relation between occupied area and logic depth respect to the previous values published in the technical literature.

Dynamically inserting, operating, and eliminating thermal sensors of FPGA-based systems

In this paper, a new thermal monitoring strategy suitable for field programmable logic array (FPGA)-based systems is developed. The main idea is that a fully digital temperature transducer can be dynamically inserted, operated, and eliminated from the circuit under test using run-time reconfiguration. A ring-oscillator together with its auxiliary blocks (basically counting and control stages) is first placed in the design. After the actual temperature of the die is captured, the value is read back via the FPGA configuration port. Then, the sensor is eliminated from the chip in order to release programmable resources and avoid self-heating. All the hardware of the sensor is written in Java, using the JBits API provided by the chip manufacturer. The main advantage of the technique is that the sensor is completely stand-alone, no I/O pads are required, and no permanent use of any FPGA element is done. Additionally, the sensor is small enough to arrange an array of them along the chip. Thus, FPGAs became a new tool for researchers interested in the thermal aspects of integrated circuits.

Thermal testing on reconfigurable computers

Ring-oscillators are useful to monitor the thermal status of reconfigurable computers. No analog parts exist, and the sensors can be dynamically inserted, moved, or eliminated.

Thermal monitoring on FPGAs using ring-oscillators

In this paper, a temperature-to-frequency transducer suitable for thermal monitoring on FPGAs is presented. The dependence between delay and temperature is used to produce a frequency drift on a ring-oscillator. Different sensors have been constructed and characterized using XC4000 and XC3000 chips, obtaining typical sensibilities of 50 kHz per °C. In addition, the utility of the Xilinx OSC4 cell as thermal transducer has been demonstrated. Although a complete temperature verification system requires a control unit with a frequency counter, the use of ring-oscillators presents several advantages: minimum FPGA elements are required; no analog parts exists; the additional hardware needed (multiplexers, prescaler, etc.) can be constructed using the resources of an FPGA, the thermal-related signals can be routed employing the standard interconnection network of the board, and finally, the sensors can be dynamically inserted or eliminated.

Ring oscillators as thermal sensors in FPGAs: Experiments in low voltage

In this paper, some experiments about thermal sensors based on ring-oscillator in low-voltage Virtex series FPGAs are presented. A non linear effect in the frequency-temperature response has been detected, and the sensibility of frequency with respect to voltage variations is greater than the measured in previous works. A quadratic polynomial function fits better the sensor response, and an increment in the number of inverters in the oscillator is effective to reduce the voltage sensibility.

Making visible the thermal behaviour of embedded microprocessors on FPGAs: a progress report

This paper shows a method to verifying the thermal status of complex FPGA-based circuits like microprocessors. Thus, the designer can evaluate if a particular block is working beyond specifications. The idea is to extract the output frequencies of an array of ring-oscillators previously distributed in the die, taking full advantage of the configuration port capabilities in Xilinx technology. As a result, it is shown that the FPGA technology offers the designers of embedded systems the possibility of viewing a detailed thermal map of a circuit at a minimum cost. The verification can be done in actual working conditions; for example with heat sinks and fans attached to the chip, inside the system case, or even in an on-board satellite application. The main results of the work are unthinkable using other alternatives like IR cameras, external sensors, or embedded diodes.

Locomotion Principles of 1D Topology Pitch and Pitch-Yaw-Connecting Modular Robots

The last few years have witnessed an increasing interest in modular reconfigurable robotics. The applications include industrial inspection (Granosik, 2005), urban search and rescue (Zhang, 2006a), space applications (Yim, 2003) and military reconnaissance (Zong, 2006). They are also very interesting for research purposes. Modular robots are composed of some identical or similar units which can attach to and detach from each other and are capable of changing the configurations. Some modular prototypes are quite famous, such as Polybot from Mark Yim (Yim, 2000), CONRO (Castano, 2000), SuperBot (Chen, 2006) from the Information Sciences Institute and Computer Science and M-TRAN robot from Japan (Kurokawa, 2003). These prototypes have two things in common. Normally this kind of robots consists of many modules which are able to change the way they are connected. In addition the modular approach enables robots the reconfiguration capability which is very essential in such tasks which are difficult for a fixed-shape robot. It also endows the mobile robotic system the characteristics of versatility, robustness, low-cost and fast-prototyping so that new configurations of different robots can be built fast and easily, for the exploration, testing and analysis of new ideas. The more exciting advantage is that the robots have the capability of adopting different kinds of locomotion to match various tasks and suit complex environments. Modular robots can be classified according to both the connection between the modules and the topology of their structure. One important group are the Snake robots, whose configurations consist of one chain of modules (1D Topology). Locomotion is performed by means of body motions. Depending on the type of connection between the modules, there are pitch, yaw and pitch-yaw connecting snake robots. The locomotion capabilities of the yaw family have been thoroughly studied (Hirose, 1993). There is also research work on the locomotion capabilities of some specific pitch-yaw modular robots. In (Chen, 2004) the rolling gaits are comprehensively studied and (Mori, 2002) implemented different gaits in the ACM robot. However, the locomotion principles for the whole pitch-yaw family have not been fully studied. In this chapter we propose a model for the locomotion of pitch-yaw snake robots that allows them to perform five different gaits: forward and backward, side-winding, rotating, rolling and turning. The rotating gait is a new one that, to the best of our knowledge has not been previously achieved by other researchers. Each joint is controlled by means of a sinusoidal O pe n A cc es s D at ab as e w w w .ite ch on lin e. co m

Locomotion of a Modular Worm-like Robot Using a FPGA-based Embedded MicroBlaze Soft-processor

Modular reconfigurable robots offer the promise of more versatility, robustness, and low cost. They are composed of simple and small modules, capable of attach and detach one to each other. In this paper, a modular worm-like robot composed of a chain of 8 similar modules is presented. A travelling wave, that moves from the tail to the head, propels the robot forward. The positions of the articulations are calculated using the following parameters: waveform, amplitude, and wavelength. Instead of a conventional architecture, a FPGA-based soft-processor core is utilized. It includes a set of custom peripheral cores, written in VHDL. FPGAs make modular robots more versatile, adding some new featureas to the design of robots like reconfigurable control, hardware reuse, lower cost, fault-recovering, and software/hardware co-design.

Rapid prototyping of a self-timed ALU with FPGAs

This article presents the design and implementation of a self-timed arithmetic logic unit (ALU) that has been developed as part of an asynchronous microprocessor. This displays an inherent operational characteristic of low consumption, owing to the synchronization signals that stop when the execution of an operation finishes (stoppable clock); that is to say, the dynamic consumption is zero, while it is not required again by an external request signal. It demonstrates the methodology of design of the self-timed controls which synchronize the data transfer, as well as the characterization of delay macros designed in FPGA editor for the adjustment of ALU processing times. It also summarizes the results of the implementation for a FPGA Virtex II, as well as the parameters of area, distribution of tracks, delay, latency, consumption and fan-out.

Low-Power FSMs in FPGA: Encoding Alternatives

In this paper, the problem of state encoding of FPGA-based synchronous finite state machines (FSMs) for low-power is addressed. Four codification schemes have been studied: First, the usual binary encoding and the One-Hot approach suggested by the FPGA vendor; then, a code that minimizes the output logic; finally, the so-called Two-Hot code strategy. FSMs of the MCNC and PREP benchmark suites have been analyzed. Main results show that binary state encoding fit well with small machines (up to 8 states), meanwhile One-Hot is better for large FSMs (over 16 states). A power saving of up to the 57 % can be achieved selecting the appropriate encoding. An area-power correlation has been observed in spite of the circuit or encoding scheme. Thus, FSMs that make use of fewer resources are good candidates to consume less power.