Jucemar Monteiro

Determination of the magnetocaloric entropy change by field sweep using a heat flux setup

We report on a simple setup using a heat flux sensor adapted to a Quantum Design Physical Property Measurement System to determine the magnetocaloric entropy change (ΔS). The major differences for the existing setups are the simplicity of this assembly and the ease to obtain the isothermal entropy change either by a field sweep or a temperature sweep process. We discuss the use of these two processes applied to Gd and Gd5Ge2Si2 samples. The results are compared to the temperature sweep measurements and they show the advantages of this setup and of the field sweep procedure. We found a significant reduction of ΔS and on the refrigerating cooling power (RCP) at low field changes in a field sweep process when the sample is not driven to the same initial state for each temperature. We show that the field sweep process without any measuring protocol is the only correct way to experimentally determine ΔS and RCP for a practical regenerative refrigerator.

Drive Strength Aware Cell Movement Techniques for Timing Driven Placement

As the interconnections dominate the circuit delay in nanometer technologies, placement plays a major role to achieve timing closure since it is a main step that defines the interconnection lengths. In initial stages of the physical design flow, the placement goal is to reduce the total wirelength, however total wirelength minimization only roughly addresses timing. A timing-driven placement incorporates timing information to remove or alleviate timing violations. In this work, we present an incremental timing-driven placement flow to further optimize timing violations via single-cell movements.For late violations, we developed techniques to reduce the load capacitance on critical nets and to obtain load capacitance balancing using drive strength. For early violations, we present techniques that rely on clock skew optimization, register swap and interconnection increase. Our flow is experimentally evaluated using the ICCAD 2015 Incremental Timing-Driven Contest infrastructure. Experimental results show that our flow can significantly reduce timing violations. On average, for long maximum displacement, the quality of results is improved by 67.8% with late WNS and TNS being improved by 2.31% and 10.84%, respectively, early WNS and TNS improved by 68.92% and 76.42%, respectively and congestion metric ABU improved by 74.9% compared to the 1st place in the contest. The impact on Steiner tree wirelength is less than 2.5%.

An Incremental Timing-Driven flow using quadratic formulation for detailed placement

In this work, we present a flow for the Incremental Timing-Driven Placement problem. Given a legal placement, the aim is to reduce the circuits timing violations without changing significantly the cell density, subject to a maximum displacement constraint. Our flow consists of two core steps: useful clock skew optimization and critical path fine tuning. During useful clock skew optimization, sequential cells are replaced, seeking to minimize clock skew. After that, a quadratic formulation is used to further reduce critical path delays. An incremental legalization tool is also presented, which supports the methods developed in this work. Our Incremental Timing-Driven Placement flow can achieve, on average, 0.3%, 26.2%, 8.7% and 23.7% of the normalized quality score improvement compared to state-of-the-art algorithms.

Rsyn: An Extensible Physical Synthesis Framework

Due to the advanced stage of development on EDA science, it has been increasingly difficult to implement realistic software infrastructures in academia so that new problems and solutions are tested in a meaningful and consistent way. In this paper we present Rsyn, a free and open-source C++ framework for physical synthesis research and development comprising an elegant netlist data model, analysis tools (e.g. timing analysis, congestion), optimization methods (e.g. placement, sizing, buffering) and a graphical user interface. It is designed to be very modular and incrementally extensible. New components can be easily integrated making Rsyn increasingly valuable as a framework to leverage research in physical design. Standard and third party components can be mixed together via code or script language to create a comprehensive design flow, which can be used to better assess the quality of results of the research being conducted. The netlist data model uses the new features of C++11 providing a simple but efficient way to traverse and modify the netlist. Attributes can be seamlessly added to objects and a notification system alerts components about changes in the netlist. The flexibility of the netlist inspired the name Rsyn, which comes from the word resynthesis. Rsyn is created to allow researchers to focus on what is really important to their research spending less time on the infrastructure development. Allowing the sharing and reusability of common components is also one of the main contributions of the Rsyn framework. In this paper, the key concepts of Rsyn are presented. Examples of use are drawn, the important standard components (e.g. physical layer, timing) are detailed and some case studies based on recent Electronic Design Automation (EDA) contests are analyzed. Rsyn is available at http://rsyn.design.

Quadratic timing objectives for incremental timing-driven placement optimization

In this work, two quadratic formulations for incremental timing-driven placement are proposed. We include the delay model formulation into the quadratic function objective. Our timing-driven quadratic techniques perform path smoothing by optimizing the distance of neighbor critical pins and balance wire load capacitance in the critical nets by reducing their total quadratic length. In our incremental quadratic techniques, the previous placement solution is kept unchanged by using the linear system neutralization operation before solving it. Our incremental quadratic timing-driven placement flow outperforms the state-of-art results by 9.4% and 7.6%, on average, regarding WNS and TNS improvement for late timing violation, respectively.

Routing-Aware Incremental Timing-Driven Placement

Meeting timing requirements and improving routability are becoming more challenging in modern design technologies. Most timing-driven placement approaches ignore routability concerns which may lead to a gap in routing quality between the actual routing and what is expected. In this paper, we propose a routing-aware incremental timing-driven placementtechnique to reduce early and late negative slacks while considering global routing congestion. Our proposed flow considers both timing and routing metrics during the detailed placement. We also presents a comprehensive analysis of timing quality score and the total number of routing overflows and the trade-off between them by modifying the International Conference on Computer Aided Design (ICCAD) 2015 timing-driven contest benchmarksand the displacement constraints. Experimental results on the ICCAD 2015 Incremental Timing-Driven Contest benchmarks show the efficacy of our proposed routing-aware incremental timing-driven placement method. On average, we obtain 22% and 17% improvement in timing quality score and global routing overflows, respectively, compared to the first placed team at 2015 ICCAD contest.

An analytical timing-driven algorithm for detailed placement

Most of recent placement algorithms are driven to HPWL minimization and routability improvement. Although timing-closure is one of the most essential aspect of the synthesis flow, few methods are currently targeting delay reduction by handling critical paths during global or detailed placement. In this work, we adapted a global placement algorithm to perform timing-aware incremental detailed placement. The analytical algorithm employed reduces, on average, by 31% and 43%, respectively, the WNS and TNS violations on all circuits and all critical path configurations after clock skew optimization, based on ICCAD 2014 benchmarks.