Marcelo de Oliveira Johann

Design of very deep pipelined multipliers for FPGAs

This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266 MHz, while the floating point unit reaches 235 MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.

Net by Net Routing with a New Path Search Algorithm

Net by net routing is still a very important technique used to make connections in VLSI circuits. The maze routing algorithms used for this purpose correspond to shortest path searches derived from basic BFS or from A*, with many dedicated improvements. This paper proposes the use of a new path search algorithm, LCS*, for routing individual connections in VLSI circuits. LCS* is a generic and simultaneous bidirectional heuristic algorithm which is faster than A* in most graph domains, such as VLSI routing grids. This is achieved by using dynamic estimation with the separation of computed values for open and closed nodes. Results show that the running time is reduced and little storage space is needed.

Effective Method for Simultaneous Gate Sizing and

This paper presents a fast and effective approach to gate-version selection and threshold voltage, Vth, assignment. In the proposed flow, first, a solution without slew and load violation is generated. Then, a Lagrangian Relaxation (LR) method is used to reduce leakage power and achieve timing closure while keeping the circuit no or few violations. If the set of gate-versions given by LR produces a circuit with negative slack, a timing recovery method is applied to find near zero positive slack. The solution without negative slack is finally introduced to a power reduction step. For the ISPD 2012 Contest benchmarks, the leakage power of our solutions is, on average, 9.53% smaller than and 12.45% smaller than . The sizing produced using our approach achieved the first place in the ISPD 2013 Discrete Gate Sizing Contest with, on average, 8.78% better power results than the second place tool. With new timing calculation applied, this flow can provide, on average, an extra 9.62% power reduction compared to the best Contest results. This flow is also the first gate sizing method to report violation-free solutions for all benchmarks of the ISPD 2013 Contest.

V

This paper addresses the problem of generating good topologies of rectilinear Steiner trees using path search algorithms. We present AMAZE, a fast maze router based algorithm that employs selected techniques to build optimized steiner trees. A biasing technique proposed for wire length improvement produces trees that are within 2% from optimal topologies in average. By introducing a sharing factor and a path-length factor we show how to trade-off wire length for delay. Our experimental results show that AMAZE is more effective to optimize delay to critical sinks than state of the art heuristics for Steiner trees, such as AHHK (from 26% to 40%) and P-Trees (from 1% to 30%) while keeping the properties of a routing algorithm. We also analyzed the ability of AMAZE to handle blockages and verified experimentally that AMAZE produces tree with better delay to the critical sinks than P-Trees from 6% (5 pin nets) to 21% (9 pin nets). An important motivation for this work lies in the fact that, due to its acceptable run time and quality of results, AMAZE can be used for estimation in the early stages as well as for actual routing, thereby improving the convergence and timing closure of the design significantly.

th Assignment Using Lagrangian Relaxation

In this paper, we address the problem of generating good topologies of rectilinear Steiner trees using path search algorithms. Various techniques have been applied in order to achieve acceptable run times on a maze router that builds Steiner trees. A biasing technique proposed for wire length improvement, produces trees that are within 2% from optimal topologies in average. By introducing a sharing factor and a path-length factor we show how to trade-off wire length for delay. Experimental results show that our algorithm generates topologies with better delay compared to state of the art heuristics for Steiner trees, such as AHHK (from 26% to 40%) and P-Trees (from 1% to 30% and from 6% to 21% in the presence of blockages) while keeping the properties of a routing algorithm. An important motivation for this work lies in the fact that it can be used for estimation in the early stages as well as for actual routing, thereby improving the convergence and timing closure of the design significantly. We also provide some valuable theoretical background and insights on delay optimization and on how it relates to our maze router implementation.

Maze routing steiner trees with effective critical sink optimization

Discrete gate sizing has attracted a lot of attention recently as the EDA industry faces the challenge of optimizing large standard cell-based circuits. The discreteness of the problem, along with complex timing models, stringent constraints and ever increasing circuit sizes make the problem very difficult to tackle. Lagrangian Relaxation is an effective technique to handle complex constrained optimization problems and therefore has been used for gate sizing. In this paper, we propose an improved Lagrangian Relaxation formulation for leakage power minimization that accounts for maximum gate input slew and maximum gate output capacitance in addition to the circuit timing constraints. We also present a fast topological greedy heuristic to solve the Lagrangian Relaxation Subproblem and a complementary procedure to fix the few remaining slew and capacitace violations. The experimental results, generated by using the ISPD 2012 Discrete Gate Sizing Contest infrastructure, show that our technique is able to optimize a circuit with up to 959K gates within only 51 minutes. Comparing to the ISPD Contest top three teams, our technique obtained on average 18.9%, 16.7% and 43.8% less leakage power, while being 38, 31 and 39 times faster.

Maze Routing Steiner Trees With Delay Versus Wire Length Tradeoff

In this paper, we present a new method for circuit legalization called Jezz, which is, on average, 42.7% better than the classic legalization algorithm Tetris in terms of overall cell displacement, and 2.4% better than Abacus, a legalization algorithm that uses a quadratic function to compute the minimum cost for moving a cell, different from Jezz, that uses a linear function. The legalization step aligns cells to sites within the circuit rows and removes any overlapping among them while trying to minimize the total displacement of cells. Jezz can perform both full and incremental legalization, indicating the impact caused by inserting a cell in a row. It intrinsically handles cell-to-site alignment and has blockage support. A cache system is used to allow fast lookup during incremental legalization, allowing Jezz to support detailed placement algorithms. Although Jezz can be 20× slower than Tetris, the full legalization of a circuit with 200k cells takes less than a second, which makes Jezz suitable even for large scale designs, as a full legalization is run just a few times during the design flow.

Fast and efficient lagrangian relaxation-based discrete gate sizing

Taking as a point of departure recent theoretical advances in Interaction Design and Human-Computer Interaction (Lowgren 2009), we discuss a body of knowledge gathered in Ubiquitous Music practices (Keller et al. 2011a) during the last six years. New concepts and methods have been proposed to describe aspects of the ideation and materialisation of experiences with technology. Pliability (Lowgren 2007) and anchoring (Keller et al. 2010) are two of the multiple design qualities that surfaced in interaction design that impact information technology creative practices. We present results of experiments addressing creativity support for ubiquitous music making through the time tagging metaphor (Radanovitsck et al. 2011). The studies serve to exemplify how relational properties can be integrated within creativity-centred design. Our research indicates that sonic relational properties may provide affordances for proto-musical phenomena. We discuss the theoretical and methodological implications of this proposal highlighting its impact on everyday musical creativity.

Jezz: An Effective Legalization Algorithm for Minimum Displacement

Discrete gate sizing has attracted a lot of attention recently as the EDA industry faces the challenge of optimizing large standard cell-based circuits. The discrete nature of the problem, along with complex timing models, stringent design constraints, and ever-increasing circuit sizes, make the problem very difficult to tackle. Lagrangian Relaxation (LR) is an effective technique to handle complex constrained optimization problems and therefore has been successfully applied to solve the gate sizing problem. This article proposes an improved Lagrangian relaxation formulation for discrete gate sizing that relaxes timing, maximum gate input slew, and maximum gate output capacitance constraints. Based on such formulation, we propose a hybrid technique composed of three steps. First, a topological greedy heuristic solves the LR formulation. Such a heuristic is applied assuming a slightly increased target clock period (backoff factor) to better explore the solution space. Second, a delay recovery heuristic reestablishes the original target clock with small power overhead. Third, a power recovery heuristic explores the remaining slacks to further reduce power. Experiments on the ISPD 2012 Contest benchmarks show that our hybrid technique provides less leakage power than the state-of-the-art work for every circuit from the ISPD 2012 Contest infrastructure, achieving up to 24% less leakage. In addition, our technique achieves a much better compromise between leakage reduction and runtime, obtaining, on average, 9% less leakage power while running 8.8 times faster.

Relational Properties in Interaction Aesthetics: The Ubiquitous Music Turn

Partitioning algorithms are responsible for the assignment of the random logic blocks and ip blocks into the different tiers of a 3D design. Cells partitioning also helps to reduce the complexity of the next steps of the physical synthesis (placement and routing). In spite of the importance of cells partitioning for the automatic synthesis of 3D designs it has been performed in the same way as in 2D designs. Graph partitioning algorithms are used to divide the cells into the different tiers without accounting for any tier location information. Due to the single dimensional alignment of the tiers connections between the bottom and top tiers have to go through all the tiers in between, e. g., in a design with five tiers a connection between the top and the bottom tiers would require four 3D-vias. 3D vias are costly in terms of routing resources and delay and therefore must be minimized. This paper presents a methodology for reducing the number of 3D-vias during the circuit partitioning step by avoiding connections between non-adjacent tiers. Our algorithm minimizes the total number of 3D-vias while respecting area balance, number of tiers and I/O pins balance. Experimental results show that the number of 3D-vias was reduced by 19%, 17%, 12% and 16% when benchmark circuits were designed using two, three, four and five tires.