Juergen Foerstner

TFSOI complementary BiCMOS technology for low power applications

A Thin-Film-Silicon-On-Insulator Complementary BiCMOS (TFSOI CBiCMOS) technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 /spl mu/m CMOS process with the lateral bipolar devices integrated as drop-in modules for CBiCMOS circuits. The near-fully-depleted CMOS device design minimizes sensitivity to silicon thickness variation while maintaining the benefits of SOI devices. The bipolar device structure emphasizes use of a silicided polysilicon base contact to reduce base resistance and minimize current crowding effects. A split-oxide spacer integration allows independent control of the bipolar base width and emitter contact spacing. Excellent low power performance is demonstrated through low current ECL and low voltage, low power CMOS circuits. A 70 ps ECL gate delay at a gate current of 20 /spl mu/A is achieved. This represents a factor of 3 improvement over bulk trench-isolated double-polysilicon self-aligned bipolar circuits. Similarly, CMOS gate delay shows a factor of 2 improvement over bulk silicon at a power supply voltage of 3.3 V. Finally, a 460 /spl mu/W 1 GHz prescaler circuit is demonstrated using this technology. >

Motorola MEMS switch technology for high frequency applications

Motorola Semiconductor Products Sector (SPS) has made significant progress in developing an integrated MEMS switch network for use in next-generation portable wireless systems. This MEMS switch technology has significantly better RF characteristics than conventional PIN diodes or FET switches and consumes less power. The RF MEMS switch exhibits insertion loss under 0.3 dB, isolation greater than 50 dB, and operating power under 200 /spl mu/W. The RF MEMS switch chip is integrated with a high voltage charge pump plus control logic chips into a single package that provides a network system to accommodate low voltage requirements in portable wireless applications.

TFSOI CMOS technology for sub-1 V microcontroller circuits

For the first time, a sub-1 V microcontroller CPU core is demonstrated using Thin-Film-Silicon-On-Insulator (TFSOI) CMOS technology. Yield sensitivity of the microcontroller circuit blocks (including the CPU, SRAM and ROM) to variations of the 0.5 /spl mu/m process technology is investigated. The low-voltage circuit yield of the CPU is found to be more sensitive to isolation stress-induced device defect leakage than the SRAM and ROM circuits. The stress-induced leakage also causes abnormal frequency vs. V/sub DD/ behavior with the CPU. CPU yield comparable to bulk CMOS, combined with a /spl sim/2/spl times/ maximum clock frequency enhancement, is achieved with the optimized low-leakage TFSOI process.

TFSOI complementary BiCMOS technology for low power RF mixed-mode applications

A Thin-Film-Silicon-On-Insulator Complementary BiCMOS technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 /spl mu/m CMOS process with the lateral bipolar device integrated as a drop-in module for CBiCMOS circuits. Excellent low power performance is demonstrated through low current ECL and low voltage CMOS circuits. For the first time, good RF and analog performance of a TFSOI (C)BiCMOS technology is demonstrated. Device gain, noise figure, 1/F noise and matching characteristics comparable to bulk BiCMOS technologies are achieved.

Materials, device and gate oxide integrity evaluation of SIMOX and bonded SOI wafers

In this paper, we will review our recent material and electrical device results on SIMOX and BESOI wafers. The substrates were obtained from 2 SIMOX suppliers (IBIS and SOITEC) and one bonded supplier (HDOS). Substrates were routinely obtained over a period of more than two years and this has given us some insight into the various manufacturers quality and reproducibility as well as improvement efforts. The material parameters such as film uniformity, contamination, defects, and wafer warp and bow will be discussed. In addition, the integrity of gate oxides grown on these substrates will be compared to those grown on bulk wafers. Device results such as threshold voltage control (Vt) and subthreshold leakage for devices built on SIMOX and BESOI wafers will be compared. These results have been obtained from several lots processed in our line and thus represent variations in both the material and the process.

Controlling the device field edge to achieve a low power TFSOI technology

The impact of stress and dopant redistribution along the field edge of SOI devices on offstate leakage, low voltage performance, and yield is discussed. For the first time, stress caused by overoxidation of the field region is shown to cause excessive device leakage and yield loss. A modified PBL isolation scheme is used to minimize this effect. Dopant redistribution is known to cause field edge leakage and is shown to contribute to narrow channel effects. A novel integration scheme is described to reduce the impact of dopant redistribution and result in a TFSOI technology suitable for low power applications.

Thin film silicon on insulator substrates and their application to integrated circuits

Thin film silicon on insulator (TFSOI) devices have been studied for years. The advantages of TFSOI devices include: a reduction in junction capacitance, potentially lower junction leakage, a simpler process, and many other well documented advantages. However, other than some military/space applications, TFSOI circuits are not currently available in commodity products. One of the reasons TFSOI circuits are not wide spread is that there has not been a reliable source of TFSOI substrates. Recently, however, several suppliers of TFSOI substrates, both SIMOX and bonded and etch-backed wafers (BESOI), have made significant improvements in their material quality and are increasing capacity to meet expected demands. In this paper, we will discuss the major materials issues and how these issues impact either the TFSOI device performance or the process integration. In addition, we will present gate oxide integrity data as well as device results from these TFSOI substrates.

Transient behaviors in partially depleted thin film SOI devices

The floating-body configuration in SOI devices is desirable because of area efficiency and parasitics reduction. It has been predicted recently that there exists a dynamic floating-body effect in partially depleted SOI devices, which can lead to transient currents during device turn-on/off. This paper presents the observed current transients due to the dynamic floating body effects. The transient behaviors are analyzed and device simulation was done to confirm our analysis.

Integrity of gate oxide on TFSOI materials

The quality of gate oxides on Thin-Film-Silicon-On-Insulator (TFSOI) substrates is essential for the development of TFSOI technologies. Compared with the extensive work on device characterization and circuit performance, however, data in this area are still limited. This paper presents a gate oxide integrity (GOI) study on both SIMOX (Separation-by-IMplantation-of-OXygen) and BESOI (Bonded-Etched-back-SOI) substrates. The effect of wafer polishing to reduce the initial surface micro-roughness is also discussed.