W.M. Huang

TFSOI complementary BiCMOS technology for low power applications

A Thin-Film-Silicon-On-Insulator Complementary BiCMOS (TFSOI CBiCMOS) technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 /spl mu/m CMOS process with the lateral bipolar devices integrated as drop-in modules for CBiCMOS circuits. The near-fully-depleted CMOS device design minimizes sensitivity to silicon thickness variation while maintaining the benefits of SOI devices. The bipolar device structure emphasizes use of a silicided polysilicon base contact to reduce base resistance and minimize current crowding effects. A split-oxide spacer integration allows independent control of the bipolar base width and emitter contact spacing. Excellent low power performance is demonstrated through low current ECL and low voltage, low power CMOS circuits. A 70 ps ECL gate delay at a gate current of 20 /spl mu/A is achieved. This represents a factor of 3 improvement over bulk trench-isolated double-polysilicon self-aligned bipolar circuits. Similarly, CMOS gate delay shows a factor of 2 improvement over bulk silicon at a power supply voltage of 3.3 V. Finally, a 460 /spl mu/W 1 GHz prescaler circuit is demonstrated using this technology. >

Comprehensive study on low-frequency noise characteristics in surface channel SOI CMOSFETs and device design optimization for RF ICs

Low-frequency (LF) noise, a key figure-of-merit to evaluate device technology for RF systems on a chip, is a significant obstacle for CMOS technology, especially for partially depleted (PD) silicon-on-insulator (SOI) CMOS due to the well-known kink-induced noise overshoot. While the dc kink effect can be suppressed by either using body contact technologies or shifting toward fully depleted (FD) operation, the noise overshoot phenomena still resides at high frequency for either FD SOI or poor body-tied (BT) SOI CMOSFETs. In this paper, floating body-induced excess noise in SOI CMOS technology is addressed, including the impact from floating body effect, pre-dc kink operation, and gate overdrive, followed by the proposal of a universal LF excess noise model. As the physical mechanism behind excess noise is identified, this paper concludes with the suggestion of a device design methodology to optimize LF noise in SOI CMOSFET technology.

TFSOI-can it meet the challenge of single chip portable wireless systems?

Tremendous progress in understanding and improving SOI material and devices has been made in recent years. The reduced junction capacitance and the minimal body-effect of SOI provides an inherent advantage for low-voltage low-power applications. Recent growth in the portable wireless communication market and the push for low cost solutions have driven the semiconductor industry into a race for the ultimate solution: a single chip radio capable of handling both the RF and baseband functions. In this paper, the applications of Thin-Film-Silicon-On-Insulator (TFSOI) to the different circuit elements of wireless communication systems are reviewed. The use of CMOS SOI devices as well as future development essential to realize the single chip radio are discussed.

AC floating-body effects in submicron fully depleted (FD) SOI nMOSFETs and the impact on analog applications

We report the impact of submicron fully depleted (FD) SOI MOSFET technology on device AC characteristics and the resultant effects on analog circuit issues. The weak DC kink and high frequency AC kink dispersion in FD SOI still degrade circuit performance in terms of distortion and low-frequency noise requirements. These issues raise concerns about FD devices for mixed-mode applications. Therefore, further device optimization such as source/drain engineering is still necessary to solve the aforementioned issues for FD SOI. On the other hand, partially depleted SOI MOSFET with body contact structures provide an alternative technology for RF/baseband analog applications.

Measurement of carrier generation lifetime in SOI devices

Abstract This paper presents a new, simple method of measuring the generation lifetime in SOI (silicon-on-insulator) MOSFETS. Lifetime is extracted from the transient characteristics of MOSFET subthreshold current. Using this technique, generation lifetime was mapped across finished SIMOX (separation by implantated oxygen) wafers, BESOI (bonded and etchedback SOI) wafers, and UNIBOND wafers. BESOI material evaluated in this study had about seven times longer effective generation lifetime than SIMOX material and the three types of the SOI wafers are shown to have a lifetime variation of ±20% across four inch wafers. The generation lifetime was also found to depend on the device fabrication process.

Low-frequency noise dependence of TFSOI BiCMOS for low power RF mixed-mode applications

Low-frequency (1/f) noise has been characterized for the first time in TFSOI BiCMOS devices designed for low power high frequency applications. In the bipolar transistors, 1/f noise obeyed a square law dependence on base current and was proportional to the inverse of the area. Aside from the expected 1/f noise, we have also observed a bias dependent generation-recombination (G/R) noise component in a small portion of these TFSOI BJTs. The 1/f noise in the near-fully-depleted MOSFETs was found to be bias independent in both the linear and saturation region of operation. However, when operated in the subthreshold regime, extraneous generation-recombination (G/R) noise becomes apparent.

TFSOI CMOS technology for sub-1 V microcontroller circuits

For the first time, a sub-1 V microcontroller CPU core is demonstrated using Thin-Film-Silicon-On-Insulator (TFSOI) CMOS technology. Yield sensitivity of the microcontroller circuit blocks (including the CPU, SRAM and ROM) to variations of the 0.5 /spl mu/m process technology is investigated. The low-voltage circuit yield of the CPU is found to be more sensitive to isolation stress-induced device defect leakage than the SRAM and ROM circuits. The stress-induced leakage also causes abnormal frequency vs. V/sub DD/ behavior with the CPU. CPU yield comparable to bulk CMOS, combined with a /spl sim/2/spl times/ maximum clock frequency enhancement, is achieved with the optimized low-leakage TFSOI process.

Floating body induced pre-kink excess low-frequency noise in submicron SOI CMOSFET technology

The well-known post-kink Lorentzian-like noise overshoot has been empirically correlated to the ac kink effect in the SOI CMOSFET in the past. This work demonstrates the existence of a 1/f/sup 2/ excess noise spectrum (<100 Hz) superimposed upon 1/f noise in partially depleted (PD) floating body SOI CMOS when devices are biased in the pre-kink region (before the dc kink onset voltage). While the impact ionization phenomenon is negligible in the pre-kink region, the new observed pre-kink excess noise provides a new insight into the body voltage instability and current fluctuation in the SOI CMOSFET.

A simple technique to measure generation lifetime in partially depleted SOI MOSFETs

This work presents a new, simple method of measuring the generation lifetime in silicon-on-insulator (SOI) MOSFETs. Lifetime is extracted from the transient characteristics of MOSFET subthreshold current. Using this technique, generation lifetime was mapped across finished SIMOX (Separation by IMplantation of OXygen) wafers and BESOI (Bonded and Etchedback SOI) wafers. BESOI material evaluated in this study had about seven times longer effective generation lifetime than SIMOX material and both the SIMOX and the BESOI are shown to have a lifetime variation of /spl plusmn/10% across four inch wafers.

Novel device lifetime behavior and hot-carrier degradation mechanisms under V/sub GS//spl ap/V/sub TH/ stress for thin-film SOI nMOSFETs

The thin-film SOI (TFSOI) MOSFET is found to have the worst device lifetime projection for a gate voltage condition of V/sub GS//spl ap/V/sub TH/ and a drain voltage below the breakdown voltage. A detailed study of the hot-carrier degradation as a function of the drain stress for this gate condition shows evidence of a transforming hot-carrier behavior and mechanism. New understanding of the dominating hot-carrier mechanisms in TFSOI MOSFETs stressed under V/sub GS//spl ap/V/sub TH/ is reported. A model of these mechanisms accounting for the observed degradation behaviors is proposed.