Juergen Koehl

An analytic net weighting approach for performance optimization in circuit placement

We propose an efficient circuit placement ap- proach based on analytic net weighting controls for nonlinear performance constraints. We justify the popular net weight- ing heuristic by first showing that an appropriate net weight- ing is a natural result of the Kuhn-Tucker conditions of cir- cuit placement optimization subject to the performance con- straints. We further give a quantitative analysis of the ef- fect of net weighting to wire length change. An effective net weighting control algorithm has been implemented and ap- plied to real chip designs. The results are very promising. A performance-optimized result can be achieved in 13.2 seconds for a chip with 1,403 circuits. An experimental CMOS chip with 45,296 circuits has a complete placement result in 40 minutes while the wire length measure is 20.3 percent better than a simulated annealing approach.

Formal verification made easy

Formal verification (FV) is considered by many to be complicated and to require considerable mathematical knowledge for successful application. We have developed a methodology in which we have added formal verification to the verification process without requiring any knowledge of formal verification languages. We use only finite-state machine notation, which is familiar and intuitive to designers. Another problem associated with formal verification is state-space explosion. If that occurs, no result is returned; our method switches to random simulation after one hour without results, and no effort is lost. We have compared FV against random simulation with respect to development time, and our results indicate that FV is at least as fast as random simulation. FV is superior in terms of verification quality, however, because it is exhaustive.

Designing mega-ASICs in nanogate technologies

This paper discusses challenges the designer faces in integrating entire system product designs, containing tens or even hundreds of millions of logic gates, into single chip solutions now within reach using circuit densities possible in the latest silicon technologies. Managing designs of this size presents a new dimension of issues, and managing the physical and electrical effects of these high density device geometries presents another; solutions in both these areas are presented. Lastly, this paper discusses the integration of multiple functional components (previously organized as systems of multiple chips from multiple design sources and technologies) into a single chip product.

A flat, timing-driven design system for a high-performance CMOS processor chipset

We describe the methodology used for the design of the CMOS processor chipset used in the IBM S/390 Parallel Enterprise Server-Generation 3. The majority of the logic is implemented by standard cell elements placed and routed flat, using timing-driven techniques. The result is a globally optimized solution without artificial floorplan boundaries. We show that the density in terms of transistors per mm/sup 2/ is comparable to the most advanced custom designs and that the impact of interconnect delay on the cycle time is very small. Compared to custom design, this approach offers excellent turn-around-time and considerably reduces overall effort.

Considering possible opens in non-tree topology wire delay calculation

Non-tree routing experiences an increasing interest as technology scales into the nanometer range. Via and wire opens have become the main yield detractors considering random spot defects due to the additive manufacturing process of copper wires. Wiring networks containing loops offer some robustness against open defects which increases functional yield. State-of-the-art delay calculation enables the treatment of loops but does not provide an adequate solution for timing analysis in the presence of an open. If the delay in the presence of an open is not properly analyzed, a functional fail will be masked and replaced by a parametric fail which is only detectable applying delay testing. In this paper we present a new method to rapidly calculate the maximum delay if an open occurs in the net. For topologies consisting of non-adjacent loops we provide proof that the worst delay considering the Elmore delay metric can be found in 2N+1 delay calculations, whereas N is the number of loops in the net.

How to process a multi million gate ASIC layout in 21 hours

This paper discusses the turn around time reduction issue for the ASIC layout design process. It reviews key technologies to reduce the runtime of several of the most time consuming design steps. It also introduces a flexible yet easy to use reference layout design flow called FastTAT that is implemented in TheGuide, an IBM ASIC design methodology tool. The layout of a 17 million gate design has been processed within 21 hours from unplaced netlist to a fully routed and timing optimized design. Practical design issues related to turn around time are also discussed.