Jeanne P. Bickford

Deep Trench Capacitor in Three Dimensional Through Silicon via Keepout Area for Electrostatic Discharge Protection

To fully enable and leverage the power of advanced processors, products must have abundant cache memory with much shorter access paths without increasing chip size. This requires growing products in the z-direction by building stacked chips (3-D chips). To optimize 3-D product costs, the area consumed by other processing requirements such as electrostatic discharge (ESD) protection needs to be as efficient as possible. Placing ESD structures made with deep trench capacitors in 3-D through silicon via keepout areas optimizes silicon area since these structures enable placement of ESD devices in space that would otherwise not be used.

Terminal metal inspection yield improvement

Power grids are designed with built in redundancy, but because of reliability concerns associated with the possibility that parts of the product power grid could require maximum current which would be constrained if any terminal metal connection is defective, all terminal metal connections in every product die are required to have 100% fully compliant terminal metal connections. The innovative method described in this paper applies an assessment of the amount of current carried by each terminal metal connection in the product die to create a map that identifies which terminal metal could be allowed to be defective and maintain product reliability and functionality. Application of this method at terminal metal connection defect inspection improves yield by taking advantage of power grid redundancy. The method identifies current carrying requirements for each TMC and creates a unique product terminal metal inspection map.

Recovering from a yield excursion: A simulated case study

Deciding when to update parameter file or floorplan yield assumptions is key to minimizing the cost impact associated with a yield excursion. Applying a yield degrade too soon creates excess inventory and applying a yield degrade too late increases the probability of missing shipments. A simulated case study is presented to aid product engineers, manufacturing engineers, and program managers in the determination of supply impacts as a function of when the yield degrade is applied. Impact is explored for both high volume and low volume products.