Juho Kim

Interleaving buffer insertion and transistor sizing into a single optimization

This work presents strategies to insert buffers in a circuit, combined with gate sizing, to achieve better power delay and area-delay tradeoffs. The purpose of this work is to examine how combining a sizing algorithm with buffer insertion will help us achieve better area delay or power-delay tradeoffs, and to determine where and when to insert buffers in a circuit, The delay model incorporates placement-based information and the effect of input slew rates on gate delays. The results obtained by using the new method are significantly better than the results given by merely using a TILOS-like gate sizing algorithm alone, as is illustrated by several area delay tradeoff curves shown in this paper.

A Security-Performance-Balanced User Authentication Scheme for Wireless Sensor Networks

The uses of wireless sensor networks have increased to be applicable in many different areas, such as military applications, ecology, and health applications. These applications often include the management of confidential information, making the issue of security one of the most important aspects to consider. In this aspect, a user authentication mechanism that allows only legitimate users to access the network data becomes critical for maintaining the confidentiality and integrity of the network information. In this paper, we describe and cryptoanalyze previous works in user authentication to illustrate their vulnerabilities and security flaws. We then propose a robust user authentication scheme that solves the identified limitations. Additionally, we describe how the proposed protocol is more suitable for a secure sensor network implementation by analysis in terms of security and performance.

JTAG Security System Based on Credentials

JTAG (Joint Test Access Group) is a powerful tool for the embedded system development environments. The features of JTAG, however, can be exploited by malicious users as a backdoor for launching attacks, an approach which now constitutes a major threat in the domain of device hacking. To deny unauthenticated users access to the features of JTAG port, this paper proposes a novel JTAG security mechanism. The proposed solution uses authentication based on credentials to achieve improved security and usability over existing solutions. Our approach is easily applicable to all standard JTAG environments because its structure is designed to be independent from the application environment. Further, the approach has lower implementation cost than encryption/decryption-based solutions since only hash and XOR calculations are employed in its authentication protocol. The security of the proposed mechanism has been verified through analysis against all forms of expected attacks, and its functionality is demonstrated with a real-life implementation.

NBTI-aware statistical timing analysis framework

Negative bias temperature instability (NBTI) has become a major factor of reliability. In this paper, we proposed a simple analytical model to predict the degraded delay distribution due to NBTI and process variation. Using our NBTI and variation-aware timing analysis framework, accurate degraded gate delay is computed without tedious simulation. Moreover, conventional variation-aware design techniques can apply to develop a reliable circuit design using our model.

Glitch elimination by gate freezing, gate sizing and buffer insertion for low power optimization circuit

One of the major factors contributing to the power dissipation in CMOS digital circuits is the switching activity. Many of such switching activities include spurious pulses, called glitches. In this paper, we propose a new method of glitch reduction by gate freezing, gate sizing, and buffer insertion. The proposed method unifies gate freezing, gate sizing, and buffer insertion into a single optimization process to maximize the glitch reduction. The effectiveness of our method is verified experimentally using LGSynth91 benchmark circuits with a 0.5/sup um/ standard cell library. Our optimization method reduces glitches by 65.64% and the power by 31.03% on average.

A Performance and Usability Aware Secure Two-Factor User Authentication Scheme for Wireless Sensor Networks

Recently, several user authentication schemes for wireless sensor networks based on two-factor concept using the smart card technology were proposed. However, they have serious limitations in terms of security and usability. First, even though they are enhancements of other works, they still have several security flaws, such as vulnerability against parallel session, privileged-insider, and gateway-node bypassing attacks and lack of mutual authentication between user station and gateway node. On the other hand, they also present a usability constraint, in a sense that they do not consider the use case when sensor nodes cannot communicate with gateway node. In this case, data collected by isolated sensor nodes could not be accessed until they recover such communication, which is in many times not recoverable rapidly or forever (e.g., military applications, natural disaster monitoring). Due to all these reasons, this paper proposes a robust user authentication scheme which fixes the security weaknesses of previous solutions and provides wider usability considering the use case when the sensor nodes cannot communicate with the gateway node. Once the solution is described, its security is ensured by formal proof and analysis against attacks. Additionally, performance and cost analysis are executed to determine its level of feasibility for real implementation.

DDoS avoidance strategy for service availability

Defending from DDoS attacks have become more difficult because they have evolved in many ways. Absence of a specific predetermined pattern, increase of number of attack devices, and distributed execution of the DDoS attack makes hard the recognition of the attack sources and thus application of countermeasures. When the DDoS attack is being executed, most of the cases, the target cannot provide its services normally; this is not a significant problem for non-critical application, but, for availability critical services such as stock financial, stock market, or governmental, the effect of the attack may involve huge damage. In this paper, we propose a DDoS avoidance strategy to provide service availability to those preregistered important users. In the proposed strategy, we divide the attack scenario in different time points and provide alternative access channels to already authenticated and other valid users.

Debug Port Protection Mechanism for Secure Embedded Devices

In this paper we propose a protection mechanism for the debug port. While debug ports are useful tools for embedded device development and maintenance, they can also become potential attack tools for device hacking in case their usage is permitted to hackers with malicious intentions. The proposed approach prevents illicit use of debug ports by controlling access through user authentication, where the device generates and issues authentication token only to the server-authenticated users. An authentication token includes user access information which represents the user’s permitted level of access and the maximum number of authentications allowed using the token. The device authenticates the user with the token and grants limited access based on the user’s access level. The proposed approach improves the degree of overall security by removing the need to expose the device’s secret key. Availability is also enhanced by not requiring server connection after the initial token generation and further by supporting flexible token transfer among predefined device groups. Low implementation cost is another benefit of the proposed approach, enabling it to be adopted to a wide range of environments in demand of debug port protection.

Statistical aging analysis with process variation consideration

As CMOS devices become smaller, process and aging variations become a major issue for circuit reliability and yield. In this paper, we analyze the effects of process variations on aging effects such as hot carrier injection (HCI) and negative bias temperature instability (NBTI). Using Monte-Carlo based transistor-level simulations including principal component analysis (PCA), the correlations between process variations and aging variations are considered. The accuracy of analysis is improved (2–7%) compared to other methods in which the correlations are ignored, especially in smaller technologies.

SERA: a secure energy reliability aware data gathering for sensor networks

Wireless sensor networks are used in many applications in military, ecology, health, and other areas. These applications often include the monitoring of sensitive information making the security issue one of the most important aspects to consider in this field. However, most of protocols optimize for the limited capabilities of sensor nodes and the application specific nature of the networks, but they are vulnerable to serious attacks. In this paper, a Secure Energy and Reliability Aware data gathering protocol (SERA) is proposed, which provides energy efficiency and data delivery reliability as well as security. The proposed protocol’s security was confirmed by a formal verification carried out using the AVISPA tool and analysis of the most common network layer attacks such as selective forwarding, sinkhole, Sybil, wormhole, HELLO flood, and acknowledgment spoofing attacks. Additionally, a visual simulation environment was developed to evaluate the performance of the proposed protocol.