Sangwoo Han

A Fully Integrated Direct-Conversion Receiver for CDMA and GPS Applications

This paper describes a fully integrated zero-IF receiver for cellular CDMA and GPS applications. The single-chip zero-IF receiver integrates the entire signal path for CDMA and GPS bands, including a low-noise amplifier (LNA), I/Q down-converters, baseband channel selection filters (CSFs), a voltage-controlled oscillator (VCO), and a local oscillator (LO) distribution circuit for each band. The cellular-band LNA achieves a noise figure (NF) of 1.2 dB, input third-order intercept point (IIP3) of 11 dBm, and gain of 15.5 dB. Cellular I/Q down-converter and baseband circuitries show 9-dB composite NF, 9 dBm IIP3 and 60-dBm input second-order intercept point (IIP2) without IIP2 calibration. The measured LO leakage is less than -110 dBm at LNA input. The phase noise of the cellular VCO is -134 dBc/Hz at 900-kHz offset with 1.76-GHz carrier frequency. Total GPS signal path achieves NF of 1.7 dB and gain of 74 dB with 42-mA current. The receiver is fabricated in a 0.35-mum SiGe BiCMOS process and packaged in a 6 mm times 6 mm 40-pin micro-lead-frame. Handset measurements report that the receiver meets or exceeds all of the CDMA-2000 requirements

A High IIP2 Direct-Conversion Receiver Using Even-Harmonic Reduction Technique for Cellular CDMA/PCS/GPS Applications

A high IIP2 direct-conversion receiver for cellular CDMA/PCS/GPS has been developed in a 0.35 mum SiGe BiCMOS process. This receiver consists of a RF front-end chip and a base-band chip. The RF front-end chip includes three LNAs, three mixer cores with a common output stage, and LO distribution blocks. The base-band chip includes a channel selection filter, an output buffer, and a DC calibration block. To achieve high IIP2 performance, an even-harmonic reduction technique is proposed based on a simplified analysis of second-order intermodulation. A 40-dB improvement of the IIP2 performance is accomplished by this technique, which reduces sensitivity to operating conditions and to output load mismatches. This receiver also attains high IIP3 and a low-noise figure. Measurement results show 71 dBm IIP2, -1.3 dBm IIP3, and 2.4 dB NF for Cellular CDMA; 68 dBm IIP2, - 3.7 dBm IIP3, and 2.9 dB NF for PCS; and 26 dBm IIP2 -30 dBm IIP3, and 2 dB NF for GPS.

A fully-integrated low power direct conversion transmitter with fractional-N PLL using a fast AFC technique for CDMA applications

The paper presents a fully integrated low power direct conversion transmitter IC for CDMA applications. To reduce the power consumption and reduce switching time, a fractional-N frequency synthesizer with an internal VCO is integrated into the transmitter IC and an N-target algorithm is proposed to implement automatic frequency calibration (AFC). Total locking time is approximately 200 /spl mu/s, including 80 /spl mu/s AFC lock time. Total current consumption for -80 dBm, -10 dBm, and 8 dBm output power are 27 mA, 33 mA, and 60 mA, respectively. This chip is housed in a small 5 mm /spl times/ 5 mm 32 pin MLF package.

A 1.2V 57mW mobile ISDB-T SoC in 90nm CMOS

This paper presents a 1.2 V 57 mW SoC using a 90 nm CMOS process in mobile ISDB-T application. This achieves −98.5 dBm sensitivity at QPSK, CR = −2/3 with 2.5 dB NF of RF tuner block and 5.6 dB C/N of OFDM block at UHF-band. To integrate RF tuner and OFDM in a small single die, a wideband single LC-VCO operating from 1.8 GHz to 3.3 GHz is proposed and OFDM is designed by hard-wired logic.

A 27.7dBm OIP3 SiGe HBT cascode LNA using IM3 cancellation technique

A 1.9GHz low noise amplifier(LNA) is implemented with SiGe BiCMOS process using a modified cascode structure. In order to achieve high linearity and low NF at the same time, the phase of IM3 (3rd order inter-modulation) in a common emitter amplifier is derived and the new IM3 cancellation method is proposed. The measurement results of the LNA at 1930MHz are gain of 16.9dB, noise figure of 1.5dB, and OIP3 of 27.7dBm with a single 2.7V supply. It consumes only 4.4mA

A Fully Integrated Low-IF Image Reject Receiver for T-DMB and DAB Applications

This paper describes a fully integrated low-IF image reject receiver for triple-band T-DMB and DAB applications. The receiver features an efficient local oscillator (LO) frequency planning using a wideband low phase noise voltage-controlled oscillator (VCO) for improved low-IF receiver performance. The tuning range of the VCO is measured from 2.65 to 3.95GHz covering all the required frequency bands (Band-II, Band-Ill, and L-Band). The receiver shows a measured noise figure (NF) of under 2dB, thereby achieving a sensitivity of lower than -100dBm with 100mW power consumption. The maximum input signal level of the receiver is lOdBm, resulting in HOdB dynamic range. Total image rejection of over 50dB is achieved. The receiver is fabricated in a 0.25-mum BiCMOS process and packaged in a 5mm x 5mm 32-pin MLF package.

A 1.8dB NF 300mW SiP for 2.6GHz diversity S-DMB application

This paper presents a 1.8V 300mW System-In-Package (SiP) solution in mobile S-DMB application. This achieves a 1.8 dB noise figure at 2.6GHz, while the measured sensitivity is −101 dBm at diversity mode. The SiP is integrated RF tuner, demodulator, SDRAM and other passive components. An internal AGC is integrated for over 100dB dynamic range. The SiP is 196 pins LFBGA and the size is 10 mm × 10 mm × 1.3 mm. The SiP consumes 300mW.

A low-voltage wideband Voltage-Controlled Oscillator for ISDB-T

A 1.2 V, 1.7 ∼ 3.4 GHz wideband Voltage-Controlled Oscillator (VCO) is proposed. To achieve the low voltage operation and wideband frequency tuning characteristic, 6-bit digitally controlled switched-capacitors bank and tunable bias circuit for four varators are used. Total tuning range is as wide as 1.6 GHz and the VCO gain (Kvco) varies from 20 MHz/V to 180 MHz/V and the measured phase noise is −102 dBc/Hz at an offset frequency of 100 kHz from a 1.8 GHz operating frequency. The VCO chip implemented using a 90 nm CMOS process has size of 420 um × 570 um and consumes 2.4 mW.

A Low-Power Cellular/PCS/WCDMA Direct-Conversion Transmitter with Enhanced VCO Remodulation Rejection

This paper presents a fully integrated low-power direct-conversion transmitter for cellular/PCS/WCDMA applications. Low-power consumption is achieved with the architecture of a simplified local-oscillator network, though the harmonics of large output signal could cause interference to the VCO. This inherent problem is effectively alleviated with a wide bandwidth fractional-N frequency synthesizer and an enhanced harmonic rejection technique. The transmitter, which consists of signal-processing blocks and a Sigma-Delta fractional-N frequency synthesizer with an integrated VCO, is fabricated using a 0.35 mum SiGe BiCMOS process. The total current consumption at minimum power is only 23 mA for the cellular and 27 mA for the PCS/WCDMA; the error vector magnitude is 3.91%, 6.98% and 8.56%, respectively.