Juinn-Dar Huang

Reactant minimization during sample preparation on digital microfluidic biochips using skewed mixing trees

Sample preparation is an indispensable process to biochemical reactions. Original reactants are usually diluted to the solutions with desirable concentrations. Since the reactants, like infants blood, DNA evidence collected from a crime scene, or costly reagents, are extremely valuable, the usage of reactant must be minimized in the sample preparation process. In this paper, we propose the first reactant minimization approach, REMIA, during sample preparation on digital microfluidic biochips (DMFBs). Given a target concentration, REMIA constructs a skewed mixing tree to guide the sample preparation process for reactant minimization. Experimental results demonstrate that REMIA can save about 31%~52% of reactant usage on average compared with three existing sample preparation methods. Besides, REMIA can be extended to tackle the sample preparation problem with multiple target concentrations, and the extended version also successfully decreases the reactant usage further.

Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping

Roth-Karp decomposition is a classical decomposition method. Because it can reduce the number of input variables of a function, it becomes one of the most popular techniques used in LUT-based FPGA technology mapping. However, the lambda set selection problem, which can dramatically affect the decomposition quality in Roth-Karp decomposition, has not been formally addressed before. In this paper, we propose a new heuristic-based algorithm to solve this problem. The experimental results show that our algorithm can efficiently produce outputs with better decomposition quality than that produced by other algorithms without using lambda set selection strategy.

Graph-based optimal reactant minimization for sample preparation on digital microfluidic biochips

Sample preparation is an essential step in biochemical reactions. Reactants must be diluted to achieve given target concentrations in sample preparation. Since some reactants like costly reagents and infants blood are valuable, their usage should be minimized during dilution. In this paper, we propose an optimal reactant minimization algorithm, GORMA, for sample preparation on digital microfluidic biochips. GORMA adopts a systematic method to exhaustively check all possible dilution solutions and then identifies the one with minimal reactant usage and waste through maximal droplet sharing. Experimental results show that GORMA outperforms all the existing methods in reactant usage. Meanwhile, the waste amount is reduced up to 30% as compared with existing waste minimization methods. Moreover, GORMA requires only 0.6% more operations on average when compared with an operation-minimal dilution method.

Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture

Roth-Karp decomposition is one of the most popular techniques for LUT-based FPGA technology mapping because it can decompose a node into a set of nodes with fewer numbers of fanins. In this paper, we show how to formulate the compatible class encoding problem in Roth-Karp decomposition as a symbolic-output encoding problem in order to exploit the feature of the two-output LUT architecture. Based on this formulation, we also develop an encoding algorithm to minimize the number of LUTs required to implement the logic circuit. Experimental results show that our encoding algorithm can produce promising results in the logic synthesis environment for the two-output LUT architecture.

Reactant and Waste Minimization in Multitarget Sample Preparation on Digital Microfluidic Biochips

Sample preparation is one of essential processes in biochemical reactions. Raw reactants are diluted in this process to achieve given target concentrations. A bioassay may require several different target concentrations of a reactant. Both the dilution operation count and the reactant usage can be minimized if multiple target concentrations are considered simultaneously during sample preparation. Hence, in this paper, we propose a multitarget sample preparation algorithm that extensively exploits the ideas of waste recycling and intermediate droplet sharing to reduce both reactant usage and waste amount for digital microfluidic biochips. Experimental results show that our waste recycling algorithm can reduce the waste and operation count by 48% and 37%, respectively, as compared to an existing state-of-the-art multitarget sample preparation method if the number of target concentrations is ten. The reduction can be up to 97% and 73% when the number of target concentrations goes even higher.

Equivalence checking of scheduling with speculative code transformations in high-level synthesis

This paper presents a formal method for equivalence checking between the descriptions before and after scheduling in high-level synthesis (HLS). Both descriptions are represented by finite state machine with datapaths (FSMDs) and are then characterized through finite sets of paths. The main target of our proposed method is to verify scheduling employing code transformations — such as speculation and common subexpression extraction (CSE), across basic block (BB) boundaries — which have not been properly addressed in the past. Nevertheless, our method can verify typical BB-based and path-based scheduling as well. The experimental results demonstrate that the proposed method can indeed outperform an existing state-of-the-art equivalence checking algorithm.

Sample preparation for many-reactant bioassay on DMFBs using common dilution operation sharing

Sample preparation is an essential processing step in most biochemical applications. Various reactants are mixed together to produce a solution with the target concentration. Since reactants generally take a notable part of the cost in a bioassay, their usage should be minimized whenever possible. In this paper, we propose an algorithm, CoDOS, to prepare the target solution with many reactants using common dilution operation sharing on digital microfluidic biochips (DMFBs). CoDOS first represents the given target concentration as a recipe matrix, and then identifies rectangles in the matrix, where each rectangle indicates an opportunity of dilution operation sharing for reactant minimization. Experimental results demonstrate that CoDOS can achieve up to 27% of reactant saving as compared with the bit-scanning method in single-target sample preparation. Moreover, even if CoDOS is not developed for multi-target sample preparation, it still outperforms the recent state-of-the-art algorithm, RSMA. Hence, it is convincing that CoDOS is a better alternative for many-reactant sample preparation.

An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping

In this paper, we propose an iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. First, it finds an area-optimized performance-considered initial network by a modified area optimization technique. Then, an iterative algorithm consisting of several resynthesizing techniques is applied to trade the area for the performance in the network gracefully. Experimental results show that this approach can provide a complete set of mapping solutions from the area-optimized one to the performance-optimized one for the given design. Furthermore, these two extreme solutions, the area-optimized one and the performance-optimized one, produced by our algorithm outperform the results of most existing algorithms. Therefore, our algorithm is very useful for the timing driven FPGA synthesis.

A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses

On an SoC bus, contentions occur while different IP cores request the bus access at the same time. Hence an arbiter is mandatory to deal with the contention issue on a shared bus system. In different applications, IPs may have real-time and/or bandwidth requirements. It is very difficult to design an arbitration algorithm to simultaneously meet these two requirements. In this paper, we propose an innovative arbitration algorithm, RB_lottery, to meet both of the requirements. It can provide not only the hard real-time guarantee but also the precise bandwidth controllability. The experimental results show that RBJottery outperforms several well-known existing arbitration algorithms.

A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication

In shared SoC bus systems, arbiters are usually adopted to solve bus contentions with various kinds of arbitration algorithms. We propose an arbitration algorithm, RT/spl I.bar/lottery, which is designed to meet both hard real-time and bandwidth requirements. For fast evaluation and exploration, we use high abstract-level models in our system simulation environment to generate parameters for our configurable arbiter. The experimental results show that RT/spl I.bar/lottery can meet all hard real-time requirements and perform very well in bandwidth allocation. The results also show that RT/spl I.bar/lottery outperforms several commonly-used arbitration algorithms today.