Jing-Yang Jou

Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing

Noise, as well as area, delay, and power, is one of the most important concerns in the design of deep submicrometer integrated circuits. Currently existing algorithms do not handle simultaneous switching conditions of signals for noise minimization. In this paper, we model not only physical coupling capacitance, but also simultaneous switching behavior for noise optimization. Based on Lagrangian relaxation, we present an algorithm which can optimally solve the simultaneous noise, area, delay, and power optimization problem by sizing circuit components. Our algorithm, with linear memory requirement and linear runtime, is very effective and efficient. For example, for a circuit of 6144 wires and 3512 gates, our algorithm solves the simultaneous optimization problem using only 2.1-MB memory and 19.4-min runtime to achieve the precision of within 1% error on a SUN Spare Ultra-I workstation.

Functional test generation for finite state machines

A functional test generation method for finite-state machines is described. A functional fault model, called the single-transition fault model, on the state transition level is used. In this model, a fault causes a single transition to a wrong destination state. A fault-collapsing technique for this fault model is also described. For each state transition, a small subset of states is selected as the faulty destination states so that the number of modeled faults for test generation is minimized. On the basis of this fault model, the authors developed an automatic test generation algorithm and built a test generation system. The effectiveness of this method is shown by experimental results on a set of benchmark finite-state machines. A 100% stuck-at fault coverage is achieved by the proposed method for several machines, and a very high coverage (>97%) is also obtained for other machines. In comparison with a gate-level test generator STG3, the test generation time is speeded up by a factor of 100.<<ETX>>

A functional fault model for sequential machines

A fault model at the state transition level is proposed for finite state machines. In this model, a fault causes the destination state of a state transition to be faulty. Analysis shows that a test set that detects all single-state-transition (SST) faults will also detect most multiple-state-transition (MST) faults in practical finite state machines. The quality of the test set generated for SST faults is close to that of the sequences derived from the checking experiment. It is also shown that the upper bound of the length of the SST fault test is 2MN/sup 2/ for an N-state M-transition machine, while that of the checking sequence is exponential. An automatic test generation algorithm and a test generation system, FTG, based on the model show that the test set generated for SST faults achieves high single stuck-at-fault coverage as well as high transistor fault coverage for multilevel implementations of the machine. >

RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction

This paper shows that the worst case switching pattern that incurs the longest bus delay while considering the RLC effect is quite different from that while considering the RC effect alone. It implies that the existing encoding schemes based on the RC model may not improve or possibly worsen the delay when the inductance effects become dominant. A bus-invert method is also proposed to reduce the on-chip bus delay based on the RLC model. Simulation results show that the proposed encoding scheme significantly reduces the worst case coupling delay of the inductance-dominated buses

A single-state-transition fault model for sequential machines

A fault model in the state transition level of finite state machines is studied. In this model, called a single-state-transition (SST) fault model, a fault causes a state transition to go to a wrong destination state while leaving its input/output label intact. An analysis is given to show that a test set that detects all SST faults will also detect most multiple-state-transition (MST) faults in practical finite state machines. It is shown that, for an N-state M-transaction machine, the length of the SST fault test set is upper-bounded by 2*M*N/sup 2/ while the length is exponential in terms of N for a checking experiment. Experimental results show that the test set generated for SST faults achieves not only a high single stuck-at fault coverage but also a high transistor fault coverage for a multilevel implementation of the machine.<<ETX>>

Equivalence checking of scheduling with speculative code transformations in high-level synthesis

This paper presents a formal method for equivalence checking between the descriptions before and after scheduling in high-level synthesis (HLS). Both descriptions are represented by finite state machine with datapaths (FSMDs) and are then characterized through finite sets of paths. The main target of our proposed method is to verify scheduling employing code transformations — such as speculation and common subexpression extraction (CSE), across basic block (BB) boundaries — which have not been properly addressed in the past. Nevertheless, our method can verify typical BB-based and path-based scheduling as well. The experimental results demonstrate that the proposed method can indeed outperform an existing state-of-the-art equivalence checking algorithm.

Communication-driven task binding for multiprocessor with latency insensitive network-on-chip

Network-on-chip is a new design paradigm for designing core based system-on-chip. It features high degree of reusability and scalability. In this paper, we propose a switch which employs the latency insensitive concepts and applies the round-robin scheduling techniques to achieve high communication resource utilization. Based on the assumptions of the 2D-mesh network topology constructed by the switch, this work not only models the communication and the contention effect of the network, but develops a communication-driven task binding algorithm that employs the divide and conquer strategy to map applications onto the multiprocessor system-on-chip. The algorithm attempts to derive a binding of tasks such that the overall system throughput is maximized. To compare with the task binding without consideration of communication and contention effect, the experimental results demonstrate that the overall improvement of the system throughput is 20% for 844 test cases.

On compliance test of on-chip bus for SOC

In this paper, we employ a monitor-based approach for on-chip bus (OCB) compliance test. To describe the OCB protocols, we propose a FSM model, which can help to extract the necessary properties systematically and verify the data part of a bus transfer efficiently. To demonstrate our methodology, we illustrate two OCB protocols, WISHBONE and AMBA AHB, as the study cases. The experimental results show that we can verify the OCB protocols efficiently and detect the design errors when tests fail.

On automatic-verification pattern generation for SoC with port-order fault model

Embedded cores are being increasingly used in the design of large system-on-a-chip (SoC). Because of the high complexity of SoC, the design verification is a challenge for system integrators. To reduce the verification complexity, the port-order fault (POF) model has been used for verifying core-based designs (Tang and Jou, 1998). In this paper, we present an automatic-verification pattern generation (AVPG) for SoC design verification based on the POF model and perform experiments on combinational and sequential benchmarks. Experimental results show that our AVPG can efficiently generate verification patterns with high POF coverage.

A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses

On an SoC bus, contentions occur while different IP cores request the bus access at the same time. Hence an arbiter is mandatory to deal with the contention issue on a shared bus system. In different applications, IPs may have real-time and/or bandwidth requirements. It is very difficult to design an arbitration algorithm to simultaneously meet these two requirements. In this paper, we propose an innovative arbitration algorithm, RB_lottery, to meet both of the requirements. It can provide not only the hard real-time guarantee but also the precise bandwidth controllability. The experimental results show that RBJottery outperforms several well-known existing arbitration algorithms.